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Ordering number : ENA1056
LC89058W-E
1. Overview
CMOS IC
Digital Audio Interface Receiver
The LC89058W-E is a digital audio interface receiver IC that demodulates signals according to a data transfer format between digital audio devices via the IEC60958/61937 and JEITA CPR-1205. It supports demodulation sampling frequencies of up to 192kHz. The LC89058W-E can easily replace the existing LC89057W-VF4A-E. The LC89058W-E incorporates a number of features for its low cost and is optimal for receiving digital data for AV amplifiers and receivers.
2. Features
2.1 Clock * Built-in PLL false lock prevention circuit to provide accurate lock. * Includes built-in oscillation amplifier and frequency divider for quartz resonator. * Output clock: 512fs, 256fs, 128fs, 64fs, 32fs, 16fs, 2fs, fs, 1/2fs, and 1/4fs. * Possible to set the oscillation amplifier (external input) clock output regardless of the PLL status. * Generates transition period signal for switching between the PLL clock and oscillation amplifier (external input) clock. * Allows the user to set the PLL clock output frequency for each sampling frequency band of input data. 2.2 Data * Can receive S/PDIF and serial data at sampling frequencies of 32kHz to 192kHz. * Equipped with a total of 7 digital data input pins: 1 input pin with an amplifier and 6 input pins with 5V tolerable TTL level signal. * Can generate data to be demodulated and through output data separately from a maximum of 7 kinds of S/PDIFs. * Equipped an S/PDIF input data detection function. Possible to monitor the data input status of 32kHz to 192kHz with microcontroller.
Continued on next page.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
N0508HKIM VL-2625 No.A1056-1/64
LC89058W-E
Continued from preceding page.
* Equipped with a serial data input pin. Possible to switch with demodulation output automatically according to the state of the PLL circuit. * The fs reception range of S/PDIF interface can be limited. LC89058W-E can be set to a no-signal input state if the reception range is exceeded. * Supports I2S data output that facilitates interfacing with DSP. 2.3 Other * Supports Multi-channel transfer and reception, using master/slave function. * Equipped with a 4bits general-purpose I/O pins. They can be used for interface with peripheral ICs. * The general-purpose I/O pins can also serve as selector inputs. Possible to switch with HDMI and XM-radio signals. * Generates a DTS-CD/LD detection flag on detection of a DTS synchronization signal. * Outputs interrupt signal for microcontroller (interrupt source can be selected). * Calculates sampling frequency of input signal and outputs it from the terminal or microcontroller interface. * Outputs IEC61937 burst preamble Pc from microcontroller interface. * Outputs IEC60958 bit 1 of channel status (non-PCM data delimiter bit). * Outputs emphasis information of channel status. * Can use up to four LC89058W-Es at the same time by setting the 2-bit chip address. * Runs on a single 3.3V power supply (S/PDIF input and microcontroller interface support 5V TTL interface.) * SQFP48 package
Package Dimensions
unit : mm (typ) 3163B
9.0 7.0 36 37 25 24
48 1 0.5 (0.75) 12 0.18
13
7.0 9.0
0.15
1.7max
0.1
(1.5)
SANYO : SQFP48(7X7)
0.5
No.A1056-2/64
LC89058W-E
4. Pin Assignment
AUDIO
MOUT
DGND
DVDD
36 35 34 33 32 31 30 29 28 27 26 25
DVDD DVDD
RERR
CKST
DGND
24 SDIN 23 SLRCK 22 SBCK 21 RDATA 20 RLRCK 19 DVDD 18 DGND 17 RBCK 16 RMCK 15 AGND 14 AVDD 13 LPF
DO 37 DI 38 CE 39 CL 40 XMODE 41 DGND 42 DVDD
43
INT
LC89058W-E
GPIO0 44 GPIO1 45 GPIO2 46 GPIO3 47 RXOUT2 48
1 2 3 4 5 6 7 8 9 10 11 12
XOUT * RX5
* RX2
* RX3
RXOUT1
DGND
DVDD
* RX0
* RX1
* RX4
* RX6
XMCK
XIN
DGND * : Pull-down resistor internal at no selection
Function
Top view
5. Pin Functions
Table 5.1 Pin Functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name RXOUT1 RX0 RX1 RX2 RX3 DGND DVDD RX4 RX5 RX6 DVDD DGND LPF AVDD AGND RMCK RBCK DGND DVDD RLRCK RDATA SBCK SLRCK SDIN O/I O O O I5 O O/I O I5(pd) I5(pd) I5(pd) I/O O I5(pd) I(pd) I5(pd) I5(pd) RX0-6 input S/PDIF through output pin 1 5V withstand voltage TTL input level compatible S/PDIF input pin (connected to GND when RX1 is set) Co-axial compatible S/PDIF input pin (supported demodulation sampling frequency of up to 96kHz) 5V withstand voltage TTL input level compatible S/PDIF input pin (connected to GND when RX1 is set) 5V withstand voltage TTL input level compatible S/PDIF input pin Digital GND Digital power supply (3.3V) 5V tolerable TTL input level compatible S/PDIF input pin 5V tolerable TTL input level compatible S/PDIF input pin 5V tolerable TTL input level compatible S/PDIF input pin Digital power supply (3.3V) Digital GND PLL loop filter connection pin Analog power supply (3.3V) Analog GND R system clock output pin (VCO, 512fs, XIN) R system bit clock I/O pin (64fs) Digital GND Digital power supply (3.3V) R system LR clock I/O pin (fs) Serial audio data output pin S system bit clock output pin (16fs, 32fs, 64fs, 128fs) S system LR clock output pin (fs/4, fs/2, fs, 2fs) External serial audio data input pin
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No.A1056-3/64
LC89058W-E
Continued from preceding page.
Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name DGND DVDD XMCK XOUT XIN DVDD DGND MOUT AUDIO CKST INT RERR DO DI CE CL XMODE DGND DVDD GPIO0 GPIO1 GPIO2 GPIO3 RXOUT2 O/I O/I O/I O/I O I/O I/O I/O I/O O O I5 I5 I5 I5 O O I I/O Digital GND Digital power supply (3.3V) Oscillation amplifier clock output pin Output pin connected to the resonator External clock input pin, connected to the resonator (12.288MHz/24.576MHz) Digital power supply Digital GND Emphasis information || Input fs monitor output || Chip address setting input pin Channel status bit 1 output || Chip address setting input pin Clock switching transition period signal output || Master/slave setting input pin Microcontroller interrupt signal output || Pins44-48 I/O setting input pin PLL lock error, data error flag output pin CCB microcontroller I/F, read data output pin (3-state) CCB microcontroller I/F, write data input pin CCB microcontroller I/F, chip enable input pin CCB microcontroller I/F, clock input pin System reset input pin Digital GND Digital power supply (3.3V) General-purpose I/O pin || Selector input pin (output referred to RDATA pin) General-purpose I/O pin || Selector input pin (output referred to RLRCK pin) General-purpose I/O pin || Selector input pin (output referred to RBCK pin) General-purpose I/O pin || Selector input pin (output referred to RMCK pin) RX0-6 input S/PDIF through output pin 2 Function
* Input voltage: I= -0.3 to 3.6V, I5 = -0.3 to 5.5V * Output voltage: O= -0.3 to 3.6V * Pins 2, 4, 5, 8, 9, 10, 24, 38, 39, 40, and 41 have an internal pull-down resistor (pd). Their level is fixed when they are unselected. * Pins 32 and 33 are input pins for chip address setting when pin 41 is held at the low level. * Pin 34 serves as the input pin for designating as the master or slave when pin 41 is held at the low level. * Pin 35 serves as the input pin for configuring the I/O of pins 44 to 47 when pin 41 is held at the low level. * The DVDD and AVDD pins must be held at the same level and turned on and off at the same timing to preclude Latch-up conditions.
No.A1056-4/64
LC89058W-E
6. Block Diagram
MOUT 32 INT 35 AUDIO 33 41 Fs calculator GPIO0 GPIO1 GPIO2 GPIO3 RXOUT2 RXOUT1 RX0 RX1 RX2 RX3 RX4 RX5 RX6 44 45 46 Cbit, Pc 47 48 1 2 3 4 5 8 9 10 PLL 16 17 Clock Divider 20 22 23 RMCK RBCK RLRCK SBCK SLRCK Input Selector Demodulation & Lock detect 36 24 Data Selector 21 RERR SDIN RDATA Microcontroller I/F XMODE
40 39 38 37
CL CE DI DO
LPF XIN XOUT XMCK
13 29 28 27 Oscillation Amplifier
Clock Selector
34 CKST
Figure 6.1 LC89058W-E Block Diagram
No.A1056-5/64
LC89058W-E
7 Common and Different Points between LC89057W-VF4A-E and LC89058W-E
7.1 Common Features Table 7.1: Common of LC89057W-VF4A-E and LC89058W-E functions (Hardware/Software Compatibility)
Item Package Supply voltage DIR reception range Oscillation amplifier input frequency 2-system-clock pin output S/PDIF inputs Serial data input Non-PCM flag output Emphasis information output DTS-CD/LD detection function General-purpose I/O Chip address setting Mode setting external resistor Microcontroller interface Register configuration SQFP48(9x9) 3.3V single source 32kHz to 192kHz 12.288MHz/24.576MHz RMCK, RBCK, RLRCK, SBCK, SLRCK 7 maximum (1 coaxial, 6 optical) SDIN AUDIO EMPHA (consumer and professional) 14-bit format detection supported 4 bits 4 addresses maximum (master/salve supported) 4 resistors used CCB (SANYO-proprietary IF) 4 command address bits, 8 data bits LC89057W-VF4A-E SBCK: 16fs, SLRCK: 1/4 output added MOUT (consumer only) LC89058W-E
7.2 Removed Functions Table 7.2: Differences between LC89057W-VF4A-E and LC89058W-E (Removed Functions)
Item Function S/PDIF unlock path switching External clock synchronization mode R and S system clock synchronization Data output format C, V, U pin output Input fs computed output Microcontroller interrupt signal LC89057W-VF4A-E Modulation and demodulation Yes Yes Asynchronous system 16, 20, 24 bits/left-justified/right-justified MSB, I S Yes 16kHz to 192kHz Yes (Low pulse, Low level output)
2
LC89058W-E Modulation removed (demodulation only) Removed Removed Synchronization clock (SELMTD, RCKSEL removed) Right-justified removed (left-justified MSB, I2S only) Removed 32kHz to 192kHz (fs < 32kHz, removed) Pulse output mode removed (level output only)
7.3 Added or Modified Functions Table 7.3: Differences between LC89057W-VF4A-E and LC89058W-E (Added or Modified Functions)
Item Oscillation amplifier initial setting PLL clock output Master clock output Clock output when XIN source Clock switching RMCK and CKST polarity S/PDIF reception limitation S/PDIF input detection range Input fs value monitor output General-purpose I/O input pin General-purpose I/O input/output pin LC89057W-VF4A-E Suspended while PLL is locked 256fs or 512fs Multiple of input fs is output No limitation Clock count is preserved (to maintain continuity) Polarity cannot be switched Reflected only to error flag. 32kHz to 96kHz (XIN=24.57M/12.28MHz) Microcontroller interface output only No timing control Parallel I/O function only LC89058W-E Permanent operation 512fs Multiple of input fs on each band is output RBCK and SBCK must 1/2 or less of RMCK Switched during the CKST pulse output Polarity can be switched Reflected to both error flag and clock output 32kHz to 192kHz (XIN=24.576MHz only) Microcontroller interface and pin outputs Polling supported (with interrupt) Internal selector input also supported. Page 19 20-26 22 23 25 23, 25 26 27 32 36 37
No.A1056-6/64
LC89058W-E
7.4 Differences in Microcontroller Registers 7.4.1 Differences in write commands Table 7.4: LC89057W-VF4A-E Write Register Map
Addr 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Setting Item All system Demodulator system Master clock R system output clock S system output clock Source switching Data input/output Output format INT source selection RERR conditions Modulation system Modulation data Test Test Test Test DI15 TESTM PBSEL1 AMPOPR1 XRLRCK1 XSLRCK1 0 RXOFF SLRCKP EMPF ERWT1 PI3 TCKSEL 0 0 0 0 DI14 0 PBSEL0 AMPOPR0 XRLRCK0 XSLRCK0 RDTMUT ROSEL2 SBCKP SLIPO ERWT0 PI2 0 0 0 0 0 DI13 TXOPR FSLIM1 EXSYNC XRBCK1 XSBCK1 RDTSTA ROSEL1 RLRCKP PCRNW FSERR PI1 TXMOD1 0 0 0 0 DI12 RXOPR FSLIM0 PLLOPR XRBCK0 XSBCK0 RDTSEL ROSEL0 RBCKP UNPCM RESTA PI0 TXMOD0 0 0 0 0 DI11 INTOPF RXMON XMSEL1 XRSEL1 PSLRCK1 0 ULSEL 0 CSRNW XTWT1 0 TXMUT 0 0 0 0 DI10 0 AOSEL XMSEL0 XRSEL0 PSLRCK0 RCKSEL RISEL2 OFSEL2 FSCHG XTWT0 VMODE TDTSEL 0 0 0 0 DI9 DOEN VOSEL XINSEL PRSEL1 PSBCK1 OCKSEL RISEL1 OFSEL1 INDET REDER VISEL TXLRP 0 0 0 0 DI8 SYSRST UOSEL PLLSEL PRSEL0 PSBCK0 SELMTD RISEL0 OFSEL0 ERROR RESEL UISEL TXDFS 0 0 0 0
Table 7.5: LC89058W-E Write Register Map
Addr 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Setting Item System setting 1 System setting 2 Master clock R system output clock S system output clock Source switching Data input/output 1 Output format INT source selection RERR condition setting General-purpose I/O Test System setting 3 Data input/output 2 Other output settings Test DI15 TESTM "0" AMPOPR1 XRLRCK1 XSLRCK1 0 "0" SLRCKP EMPF ERWT1 PI3 "0" 0 0 FSSEL1 0 DI14 0 "0" AMPOPR0 XRLRCK0 XSLRCK0 RDTMUT ROSEL2 SBCKP GPIO ERWT0 PI2 0 0 RXSEL2 FSSEL0 0 DI13 "0" FSLIM1 "0" XRBCK1 XSBCK1 RDTSTA ROSEL1 RLRCKP PCRNW FSERR PI1 "0" CKSTP RXSEL1 0 0 DI12 "0" FSLIM0 PLLOPR XRBCK0 XSBCK0 RDTSEL ROSEL0 RBCKP UNPCM RESTA PI0 "0" RMCKP RXSEL0 0 0 DI11 "0" RXMON XMSEL1 XRSEL1 PSLRCK1 0 "0" 0 CSRNW "0" 0 "0" 0 EDTMUT PTOXW1 0 DI10 0 AOSEL XMSEL0 XRSEL0 PSLRCK0 0 RISEL2 "0" FSCHG "0" "0" "0" PLLDV1 EMCKP PTOXW0 0 DI9 DOEN "0" XINSEL PRSEL1 PSBCK1 OCKSEL RISEL1 "0" INDET REDER "0" "0" PLLDV0 EXTSEL 0 0 DI8 SYSRST MOSEL "0" PRSEL0 PSBCK0 0 RISEL0 OFDSEL ERROR RESEL "0" "0" PLLACC GPIOS 0 0
* Except MOSEL, PRSEL [1:0], OFDSEL, GPIO, SELMTD and RCKSEL, the command address of any inadvertently specified commands that are removed from the LC89057W-VF4A-E is assumed to be "0" and ignored. The new commands added to the LC89058W-E are allocated to command addresses 12, 13, and 14.
No.A1056-7/64
LC89058W-E
7.4.2 Differences in read commands Table 7.6: Changes in the Register Function between LC89057W-VF4A-E and LC89058W-E
CCB Address 0xE9 LC89057W-VF4A-E DIT channel status write register LC89058W-E Removed
Table 7.7: Differences in Read Registers between the LC89057W-VF4A-E and LC89058W-E
LC89057W-VF4A-E Register DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 DO9 DO10 DO11 DO12 DO13 DO14 DO15 DO16 DO17 DO18 DO19 DO20 DO21 DO22 DO23 0xEA RXDET0 RXDET1 RXDET2 RXDET3 RXDET4 RXDET5 RXDET6 RXDET7 OERROR OINDET OFSCHG OCSRNW OUNPCM OPCRNW OSLIPO OEMPF CSBIT1 IEC1937 DTS51 DTSES F0512 F1024 F2048 F4096 0xEB PO0 PO1 PO2 PO3 FSC0 FSC1 FSC2 FSC3 FSDAT0 FSDAT1 FSDAT2 FSDAT3 FSDAT4 FSDAT5 FSDAT6 FSDAT7 0xEA RXDET0 RXDET1 RXDET2 RXDET3 RXDET4 RXDET5 RXDET6 0 OERROR OINDET OFSCHG OCSRNW OUNPCM OPCRNW OGPIO OEMPF CSBIT1 IEC1937 DTS51 DTSES 0 0 0 0 LC89058W-E 0xEB PO0 PO1 PO2 PO3 FSC0 FSC1 FSC2 FSC3 -
* The CCB addresses 0xEC and 0xED remain the same for both the LC89057W-VF4A-E and LC89058W-E.
No.A1056-8/64
LC89058W-E
7.5 Points to Notice about Replacing * When replacing the LC89057W-VF4A-E with the LC89058W-E, it may be necessary to review the circuit pattern design of the printed circuit board in advance depending how the device is used. Particular attention should be directed to pins 44 to 48 whose I/O functionality can be set according to the INT pin setting. This section contains the notes and cautions to be observed when replacing the LC89057W-VF4A-E with the LC89058W-E. For details of the INT pin, see Chapter 9, Initial System Settings and Chapter 10, Description of Demodulation Function. * Refer to the specifications of LC89057W-VF4A-E when replacing LC89058W-E with LC89057W-VF4A-E. Table 7.8: Differences between LC89057W-VF4A-E and LC89058W-E (Pins 44 to 48)
INT Pin LC89057W-VF4A-E Modulation function Pull-down Pin.44 TMCK Input Pin.45 TBCK Input Pin.46 TLRCK Input Pin.47 TDATA Input Pin.48 TXO Output Pin.44 GPIO0 Input LC89058W-E General-purpose I/O function Pin.45 GPIO1 Input Pin.46 GPIO2 Input Pin.47 GPIO3 Input S/PDIF Pin.48 RXOUT2 Output S/PDIF Pin.47 GPIO3 Output Pin.48 RXOUT2 Output
General-purpose I/O function Pull-up Pin.44 PIO0 In/Output Pin.45 PIO1 In/Output Pin.46 PIO2 In/Output Pin.47 PIO3 In/Output Pin.48 PIOEN Input Pin.44 GPIO0 Output
General-purpose I/O function Pin.45 GPIO1 Output Pin.46 GPIO2 Output
7.5.1 Change from LC89057W-VF4A-E to LC89058W 7.5.1 When the INT pin is set to pull-down
Print Board LC89057W-VF4A-E INT Pin. 35 INT LC89058W-E Pin. 35
TMCK TBCK TLRCK TDATA TXO
Pin. 44 Pin. 45 Pin. 46 Pin. 47 Pin. 48
GPIO0 GPIO1 GPIO2 GPIO3 RXOUT2
Pin. 44 Pin. 45 Pin. 46 Pin. 47 Pin. 48
Figure 7.1 Change from LC89057W-VF4A-E to LC89058W-E (when the INT pin is set to pull-down) * In this case, the system that doesn't use a modulation function or a general-purpose I/O function can be replaced with LC89058W-E. * After the replacement, LC89058W-E is used on condition that it pins 44 to 47 connect with GND and pin 48 open.
No.A1056-9/64
LC89058W-E
7.5.1.2 When the INT pin is set to pull-up 7.5.1.2.1 In case of "Pin 48 = GND"
Print Board LC89057W-VF4A-E INT INT LC89058W-E
Pin. 35
Pin. 35
PIO0 PIO1 PIO2 PIO3 PIOEN JP
Pin. 44 Pin. 45 Pin. 46 Pin. 47 Pin. 48
GPIO0 GPIO1 GPIO2 GPIO3 RXOUT2
Pin. 44 Pin. 45 Pin. 46 Pin. 47 Pin. 48
Open when LC89058W-E use
Figure 7.2 Change from LC89057W-VF4A-E to LC89058W-E (when the INT pin is set to pull-up) 1 * After the replacement, pins 44 to 47 can be used as general purpose I/O output function. (pin 48 open) * It is necessary to review the circuit pattern of the printed circuit board because the I/O setting of pin 48 differs from each other. 7.5.1.2.2 In case of "Pin 48 = VDD"
Print Board LC89057W-VF4A-E JP INT INT PIO0 PIO1 PIO2 PIO3 LC89058W-E Pin. 35
Pin. 35 Pin. 44 Pin. 45 Pin. 46 Pin. 47 GPIO0 GPIO1 GPIO2 GPIO3 RXOUT2
Pin. 44 Pin. 45 Pin. 46 Pin. 47 Pin. 48
PIOEN Pin. 48 JP Open when LC89058W-E use
Figure 7.3 Change from LC89057W-VF4A-E to LC89058W-E (when the INT pin is set to pull-up) 2 * It is necessary to review the circuit pattern of the printed circuit board to change the pull-up resistor of pin 35 to the pull-down resistor because pins 44 to 47 is used as general purpose I/O input function. * It is necessary to review the circuit pattern of the printed circuit board because the I/O setting of pin 48 differs from each other.
No.A1056-10/64
LC89058W-E
7.5.2 Change from LC89058W-E to LC89057W-VF4A-E 7.5.2.1 When the INT pin is set to pull-down
Print Board LC89058W-E JP INT INT GPIO0 GPIO1 GPIO2 GPIO3 RXOUT2 LC89057W-VF4A-E Pin. 35
Pin. 35 Pin. 44 Pin. 45 Pin. 46 Pin. 47 Pin. 48
PIO0 PIO1 PIO2 PIO3 PIOEN
Pin. 44 Pin. 45 Pin. 46 Pin. 47 Pin. 48
JP Short when LC89057W-VF4A-E use
Figure 7.4 Change from LC89058W-E to LC89057W-VF4A-E (when the INT pin is set to pull-down) * It is necessary to review the circuit pattern of the printed circuit board to change the pull-up resistor of pin 35 to the pull-down resistor because pins 44 to 47 is used as general purpose I/O input function. * It is necessary to review the circuit pattern of the printed circuit board because the I/O setting of pin 48 differs from each other. * After the replacement, the RXOUT2 output of LC89057W-VF4A-E cannot be used. 7.5.2.2 When the INT pin is set to pull-up
Print Board LC89058W-E INT INT LC89057W-VF4A-E
Pin. 35
Pin. 35
GPIO0 GPIO1 GPIO2 GPIO3 RXOUT2 JP
Pin. 44 Pin. 45 Pin. 46 Pin. 47 Pin. 48
PIO0 PIO1 PIO2 PIO3 PIOEN
Pin. 44 Pin. 45 Pin. 46 Pin. 47 Pin. 48
Short when LC89057W-VF4A-E use
Figure 7.5 Change from LC89058W-E to LC89057W-VF4A-E (when the INT pin is set to pull-up) * After the replacement, pins 44 to 47 can be used as general purpose I/O output function. However, it is necessary to review the circuit pattern of printed circuit board because pin 48 has to GND. * After the replacement, the RXOUT2 output of LC89057W-VF4A-E cannot be used.
No.A1056-11/64
LC89058W-E
8. Electrical Characteristics
8.1 Absolute Maximum Ratings Table 8.1: Absolute Maximum Ratings at AGND = DGND = 0V
Parameter Maximum supply voltage Maximum supply voltage Input voltage 1 Input voltage 2 Output voltage Storage ambient temperature Operating ambient temperature Maximum input/output current Symbol AVDD max DVDD max VIN1 VIN2 VOUT Tstg Topr IIN, IOUT 8-1-6 8-1-1 8-1-2 8-1-3 8-1-4 8-1-5 Conditions Ratings -0.3 to +4.6 -0.3 to +4.6 -0.3 to VDD+0.3 (max.3.9V) -0.3 to +5.8 -0.3 to VDD+0.3 (max.3.9V) -55 to +125 -30 to +70 20 Unit V V V V V C C mA
8-1-1: AVDD pin 8-1-2: DVDD pin 8-1-3: RX1, RBCK, RLRCK, XIN, GPIO0, GPIO1, GPIO2, GPIO3 pins 8-1-4: RX0, RX2, RX3, RX4, RX5, RX6, SDIN, DI, CE, CL, XMODE pins _________ 8-1-5: RXOUT1, RMCK, RBCK, RLRCK, RDATA, SBCK, SLRCK, XMCK, XOUT, MOUT, AUDIO pins, _____ CKST, INT, RERR, DO, GPIO0, GPIO1, GPIO2, GPIO3, RXOUT2 pins 8-1-6: Per input/output pin 8.2 Allowable Operating Ranges Table 8.2: Recommended Operating Conditions at AGND = DGND = 0V
Parameter Supply voltage Input voltage range 1 Input voltage range 2 Operating temperature Symbol AVDD, DVDD VIN1 VIN2 Topr 8-2-1 8-2-2 Conditions Ratings min 3.0 0 0 -30 typ 3.3 3.3 3.3 max 3.6 AVDD, DVDD 5.5 70 Unit V V V C
8-2-1: RX1, RBCK, RLRCK, XIN, GPIO0, GPIO1, GPIO2, GPIO3 pins 8-2-2: RX0, RX2, RX3, RX4, RX5, RX6, SDIN, DI, CE, CL, XMODE pins
No.A1056-12/64
LC89058W-E
8.3 DC Characteristics Table 8.3: DC Characteristics at Ta = -30 to 70C, AVDD = DVDD = 3.0 to 3.6V, AGND = DGND = 0V
Parameter Input, High Input, Low Input, High Input, Low Output, High Output, Low Output, High Output, Low Output, High Output, Low Output, High Output, Low Input amplitude Consumption current Pull-down resistance Symbol VIH VIL VIH VIL VOH VOL VOH VOL VOH VOL VOH VOL VPP IDD RDN 8-3-7 8-3-8 8-3-9 25 50 200 40 100 8-3-6 VDD-0.8 0.4 8-3-5 VDD-0.8 0.4 8-3-4 VDD-0.8 0.4 8-3-3 8-3-2 2.0 -0.3 VDD-0.8 0.4 8-3-1 Conditions min 0.7VDD 0.2VDD 5.8 0.8 Ratings typ max V V V V V V V V V V V V mV mA k Unit
8-3-1: CMOS compatible: RBCK, RLRCK input pins during XIN and slave settings 8-3-2: TTL compatible: Input pins other than those listed above 8-3-3: IOH = -12mA, IOL = 8mA: RMCK output pin 8-3-4: IOH = -8mA, IOL = 8mA: XOUT, XMCK output pins 8-3-5: IOH = -4mA, IOL = 4mA: RXOUT1, RBCK, RLRCK, RDATA, SBCK, SLRCK, RERR, MOUT, GPIO0, GPIO1, GPIO2, GPIO3, RXOUT2 output pins 8-3-6: IOH = -2mA, IOL = 2mA: Output pins other than those listed above 8-3-7: Before capacitance of RX1 input pin, and reception frequency is possible up to 96kHz. 8-3-8: Ta=25C, fs=96kHz 8-3-9: RX0, RX2, RX3, RX4, RX5, RX6 input pins
No.A1056-13/64
LC89058W-E
8.4 AC Characteristics Table 8.4: AC Characteristics at Ta=-30 to 70C, AVDD=DVDD=3.0 to 3.6V, AGND=DGND=0V
Parameter RX0, RX2 to RX6 fs frequency RX1 fs frequency RX0, RX2 to RX6 pulse width RX1 pulse width RX0 to RX6 duty factor XIN clock frequency RMCK clock frequency RMCK clock jitter RMCK, RBCK delay RBCK, RDATA delay RMCK, SBCK delay SBCK, RDATA delay Symbol fRFS1 fRFS2 tWDI1 tWDI2 tDUY fXF fMCK tj tMBO tBDO tMBO tBDO 8-4-2 8-4-3 8-4-1 Conditions min 28 28 20 40 40 12 4 200 10 10 10 10 60 25 50 Ratings typ max 195 108 kHz kHz ns ns % MHz MHz ps ns ns ns ns Unit
8-4-1 A frequency compatible with the XINSEL setting must be applied to XIN. 8-4-2: When RMCK and SBCK source clocks are identical 8-4-3: When SBCK is the PLL source clock
RX0-6 (I) RMCK (O) (RMCKP=0) RBCK (O) RLRCK (O) RDATA (O)
tWDI tWDI tDUY
tDUY
FMCK tBDO
tMBO
Figure 8.1 AC Characteristics of Demodulation function
No.A1056-14/64
LC89058W-E
8.5 CCB Microcontroller Interface AC Characteristics Table 8.5: CCB Microcontroller Interface AC Characteristics at Ta=-30 to 70C, AVDD=DVDD=3.0 to 3.6V, AGND=DGND=0V
Parameter XMODE pulse width, Low CL pulse width, Low CL pulse width, High CL, CE setup time CL to CE hold time CL to CE hold time CL, DI setup time CL, DI hold time CL, CE hold time CL, DO delay time CE, DO delay time Symbol tRST dw tCL dw tCL uw tCE setup tCE hold tCE hold tDI setup tDI hold tCL hold tCL to DO tCE to DO 8-5-1 8-5-2 Conditions min 200 100 100 50 50 0 50 50 50 20 20 Ratings typ max s ns ns ns ns ns ns ns ns ns ns Unit
8-5-1: CL has to lower before CE is H when CL is normal H clock. 8-5-2: Only when data write with CL of normal H clock.
tCLuw CL (I)
tCLdw
tCEsetup CE (I) tDIsetup DI (I) tCEtoDO DO (I) Hi-Z tCLtoDO tCEhold tDIhold tCLhold
Figure 8.2 CCB Microcontroller Interface AC Characteristics
No.A1056-15/64
LC89058W-E
9. Initial System Settings
9.1 System Reset (XMODE) * The system operates correctly when XMODE is set to "H" after 3.0V or higher supply voltage is applied. When XMODE is set to "L" after power is turned on, the system is reset. * To set chip address, master/slave, or pins 44 to 47 I/O, 10k pull-down or pull-up resistors must be connected to MOUT, AUDIO , CKST, and INT . * If none of MOUT, AUDIO , CKST, and INT are pulled down or pulled up, their pin state will get unstable when the settings are entered, resulting in wrong setting. Pull-up or pull-down resistors must be connected to these pins without fail. Table 9.1: Pin Names and Settings
Setting Chip address Master/slave setting Pins 44 to 47 I/O setting Pins MOUT AUDIO CKST INT
Normal system operation range Setting completed 3.0V DVDD t t > 200s XMODE Resetting Setting completed
Set pin state
Undefined
Setting input state
Output state
Setting input state
Output state
Figure 9.1 Setting Timing Chart of Function Setting Input Pins
Table 9.2: Output Pin State When XMODE is Reset (XMODE=L)
No. 1 16 17 20 21 22 23 27 Pin name RXOUT1 RMCK RBCK RLRCK RDATA SBCK SLRCK XMCK Pin State RXO output XIN output Low output High output Low output Low output High output XIN output No. 32 33 34 35 36 37 48 Pin name MOUT AUDIO CKST INT RERR DO RXOUT2 Pin State Input state Input state Input state Input state High output Hi-z output Low output
No.A1056-16/64
LC89058W-E
___________
9.2 Chip Address Settings (MOUT, AUDIO) * The LC89058W-E comes with a function to set a unique chip address to allow the use of several LC89058W-E on the same microcontroller interface bus. ____________ * In chip address setting, connect a 10k pull-down or pull-up resistor to MOUT and AUDIO. By this setting, 4 kinds of chip addresses can be set at a maximum. * Chip addresses in the microcontroller interface are set with CAL and CAU provided as the first two bits on the LSB side. CAL corresponds to the lower chip address and CAU to the higher chip address. ____________ * Command writing is enabled by making the chip address settings with MOUT and AUDIO identical to the chip addresses sent from the microcontroller. * The chip address setting is required even when only one LC89058W-E is used in the system. If the chip address is not set, the chip address is undefined and the microcontroller cannot control the system. When the microcontroller is not used, a chip address-setting pin____________ open while XMODE is "L". Be sure to connect either a pull-down resistor or a is input pull-up resistor to MOUT and AUDIO.
_____ AUDIO Pull-down Pull-down Pull-up Pull-up
Table 9.3: Chip Address Settings (Resistor Connection)
MOUT Pull-down Pull-up Pull-down Pull-up CAU 0 0 1 1 CAL 0 1 0 1
LC89058W-E
MOUT AUDIO CKST INT
pull-up 10k
Connect to different circuits
pull-down 10k
Setting Contents of Above Figure Chip address setting Master or slave setting Pins 44 to 47 input or output setting CAL=CAU=0 Master Pins 44 to 47 output pins
Figure 9.2 Setting Example of Function Setting Input Pin
No.A1056-17/64
LC89058W-E
9.3 Master/Slave Settings (CKST) * A master/slave function that allows multi-channel synchronized transfer using multiple LC89058W-Es is included. For this setting, connects either a 10k pull-down or a pull-up resistor to CKST. * Set to the master mode normally, when single LC89058W-E IC is used. When multiple LC89058W-Es are used, set one of them to the master mode and the others to the slave mode. * In the multi-channel synchronous transfer mode using multiple LC89058W-Es, connect RBCK and RLRCK (output) on the master side to RBCK and RLRCK (input) on the slave side. Also connect XMCK on the master side to XIN on the slave side. At this time, the polarity of RBCK and RLRCK, and the frequency of XIN and XMCK must be identical. * The master/slave function runs correctly with the multiple LC89058W-Es connected. * Be sure to connect either a pull-down resistor or a pull-up resistor to CKST. * Always supply the clock to RBCK and RLRCK when the slave function is set. Table 9.4: Master/Slave Switching (Register Connection)
CKST Pull-down Pull-up Mode Master Slave
Table 9.5: Clock Pin State
Pin RMCK RBCK RLRCK Master mode Output Output Output Slave mode Output Input Input
9.4 Pins 44 to 47 I/O settings ( INT ) * Pins 44 to 47 are provided with a bidirectional buffer. * When setting I/O function of pins 44 to 47, connect a 10k pull-down or pull-up resistor to INT . * Be sure to connect either a pull-down resistor or a pull-up resistor to INT . Table 9.6: Pins 44 to 47 I/O Settings (Resistor Connection) ___
INT Pull-down Pull-up Mode Input. Output.
No.A1056-18/64
LC89058W-E
10 Description of Demodulation Function
10.1 Clocks 10.1.1 PLL (LPF) * The LC89058W-E incorporates a VCO (Voltage Controlled Oscillator) that can be stopped with PLLOPR and it synchronizes with sampling frequencies (fs) from 32kHz to 192kHz and with the data with transfer rate from 4MHz to 25MHz. PLL is locked at 512fs. * LPF is a pin for PLL loop filter. Connect the following resistance and capacitance shown in the figure.
LPF
R0 C0
C1 R0 : 220 C0 : 0.1F C1 : 0.022F
Figure 10.1 Loop Filter Configuration 10.1.2 Oscillation amplifiers (XIN, XOUT, XMCK) * The LC89058W-E features a built-in oscillation amplifier. Connecting a quartz resonator, feedback resistor, and load capacitance to XIN and XOUT can configure an oscillation circuit. When connecting a quartz resonator, use one with a fundamental wave. Be aware that the load capacitance depends on the quartz resonator characteristics. * If the built-in oscillation amplifier is not used and oscillation module is used as the clock source instead, connect the output of an external clock supply source to XIN. At this time, it is not necessary to connect a feedback resistor between XIN and XOUT. * Always supply XIN with the 12.288MHz or 24.576MHz clock set with XINSEL. If supplying other frequencies to XIN, it is necessary to set that the result of change in sampling frequency fs of input data with FSERR is not reflected to an error flag. By this setting, the operation functions properly. Since it is not a recommended frequency, it cannot be used for input fs calculations. * The setting of XINSEL must be completed prior to S/PDIF input. * Supply XIN with clocks all the time to be used in the following applications. (1) Detection of presence or absence of S/PDIF input (2) Clock source while PLL is unlocked (3) Calculation of input data sampling frequency (4) Time definition when switching input data (5) External source of supply clock (clock for an AD converter, etc.) in XIN source mode. (6) Polling processing performed when setting the general-purpose I/O input function * The oscillation amplifier runs even when the PLL is locked. Therefore, data detection and calculation of input sampling frequency become possible while the PLL is locked. In that case, both the oscillation amplifier clock and the PLL clock signals coexist, and then user must pay attention and make sure sound quality is not adversely affected. * If adverse effects on the sound quality are recognized, it is possible to set with the AMPOPR [1:0] that the oscillation amplifier automatically stop operation while the PLL is locked. Therefore, setting of the AMPOPR [1:0] must be completed either prior to S/PDIF input or while PLL is unlocked. * The oscillation amplifier can be stopped if it is unnecessary. However, when the normal operation is resumed, it must wait for 10ms or longer until the resonator oscillation gets stable. * XMCK outputs the XIN clock. The XMCK output is set with XMSEL [1:0]. The XIN clock can be set to 1/1, 1/2, 1/4, or muted output. * If you use only the oscillation amplifier, input the quartz resonator to XIN and XOUT or an external clock to XIN, and fix the electric potential of digital data input pins of RX0 to RX6, or set with RISEL [2:0] that all the inputs are deselected.
No.A1056-19/64
LC89058W-E
10.1.3 Switching between master clock and clock source * The RMCK, RBCK, and RLRCK (hereunder, R system), and the SBCK and SLRCK (hereunder, S system) clock sources can be selected between the following two master clocks. (1) PLL source (512fs) (2) XIN source (12.288MHz or 24.576MHz) * Clock source switching is to set with the R and S systems interlocked. This setting is carried out with OCKSEL. * The clock source is automatically switched to the PLL or XIN clock by locking/unlocking the PLL. The clock source can be switched to XIN with OCKSEL, regardless of the PLL status. Table 10.1: Relationship between Clock Source Switch Commands and Clock Sources when PLL Locked/Unlocked
OCKSEL 0 1 R System Clock Source Locked PLL XIN Unlocked XIN XIN S System Clock Source Locked PLL XIN Unlocked XIN XIN
* The PLL status can be always monitored with RERR even after switching to the XIN source. Moreover, the processed information can be read with the microcontroller interface regardless of the PLL status. 10.1.4 Points to notice about switching clock source while PLL is locked * It is necessary to set the oscillation amplifier to the continuous operation mode at the same time with AMPOPR [1:0] to do the clock switch to the XIN source with OCKSEL when the oscillation amplifier has stopped in the state where the PLL is locked. The clock is not output when switching to the XIN clock source without executing this setting. * In the state where the PLL is locked, if the clock is switched to XIN source with OCKSEL while the oscillator amplifier is stopped, RERR is temporarily outputs an error (high level) indication. When switched to XIN source, the oscillator amplifier is switched to the operating state at the same time. RERR is temporality outputs an error (H level) indication when the oscillation amplifier switches from the stop condition to the continuous mode. Consequently the input fs calculation restarts. At this time, the previous fs calculation value is reset and compared with the newly calculated fs value. Then those two values are found not identical, that's why the error is temporarily issued.
No.A1056-20/64
LC89058W-E
10.1.5 Master clock block diagram (XIN, XOUT, RMCK, XMCK) * The relationships between the two types of PLL and XIN source master clocks, switching, and the frequency division function are described below. * The contents in the quotation marks "*** " by the switch and function blocks correspond to the write command names. * Lock/Unlock is automatically switched by PLL locking/unlocking.
"PLLOPR" S/PDIF PLL 512fs
"PLLDV1" "PLLDV2" Auto 1/N (N=1,2,4) "PLLACC"
Lock/Unlock
1/N (N=1,2,4) XOUT "PRSEL[1:0]" "XINSEL" XIN "AMPOPR[1:0]" GPIO0 12.288M 24.567M "XRSEL[1:0]" 1/N (N=1,2,4)
"OCKSEL"
"RMCKP"
RMCK
"EXTSEL" "EMCKP" "XMSEL[1:0]" 1/N (N=1, 2) XMCK
Figure 10.2 Master Clock Block Diagram
No.A1056-21/64
LC89058W-E
10.1.6 PLL clock output * The PLL clock output is controlled by the PLLACC, PLLDV1, PLLDV2, or PRSEL[1:0]. * PLLACC can be used to generate a PLL lock frequency for each S/PDIF input sampling frequency band.
S/PDIF Input
512fs Lock detection Lock Fs calculation
Unlock
PLL output Free-run
*: When the data is judged to exceed the value of FSLIM [1:0] which limits the reception frequency of the input S/PDIF, processing similar to PLL unlocking is carried out and the processing does not proceed to the subsequent step. The clock source is automatically switched to the XIN source.
* 0 "PLLACC" 1 PLL fixation output "PRSEL=00": 256fs "PRSEL=01": 512fs "PRSEL=10": 128fs
Fs= 32k, 44.1k, 48k Yes
No
Fs= 64k, 88.2k, 96k 0 Yes
No
"PLLDV0" 1
Fs= 128k, 176.4k, 192k 0 Yes PLL output 128fs
No
"PLLDV1" PLL output 256fs PLL output 512fs 1 PLL output 512fs PLL output 256fs
PLL output 256fs
Figure 10.3 PLL Clock Output Control Table 10.2: PLL Clock Output Frequencies (Bold settings are recommended values.)
PLL Output S/PDIF fs PLLACC=0 (Fixed multiple outputs of input fs) PRSEL=00 (256fs) 32kHz 44.1kHz 48kHz 64kHz 88.2kHz 96kHz 128kHz 176.4kHz 192kHz 8.19MHz 11.28MHz 12.28MHz 16.38MHz 22.57MHz 24.57MHz 32.76MHz 45.15MHz 49.15MHz PRSEL=01 (512fs) 16.38MHz 22.57MHz 24.57MHz 32.76MHz 45.15MHz 49.15MHz 65.53MHz 90.31MHz 98.30MHz PRSEL=10 (128fs) 4.09MHz 5.64MHz 6.14MHz 8.19MHz 11.28MHz 12.28MHz 16.38MHz 22.57MHz 24.57MHz PLLACC=1 (Fixed multiple outputs for each input fs band) PLLDV0=0 PLLDV1=0 16.38MHz 22.57MHz 24.57MHz 16.38MHz 22.57MHz 24.57MHz 16.38MHz 22.57MHz 24.57MHz PLLDV0=1 PLLDV1=0 8.19MHz 11.28MHz 12.28MHz 16.38MHz 22.57MHz 24.57MHz 16.38MHz 22.57MHz 24.57MHz PLLDV0=0 PLLDV1=1 16.38MHz 22.57MHz 24.57MHz 32.76MHz 45.15MHz 49.15MHz 16.38MHz 22.57MHz 24.57MHz PLLDV0=1 PLLDV1=1 8.19MHz 11.28MHz 12.28MHz 32.76MHz 45.15MHz 49.15MHz 16.38MHz 22.57MHz 24.57MHz
* If 128kHz, 176.4kHz or 192kHz input is received when the PLLACC is set to 0 and the PRSEL [1:0] to 01, the DC characteristics of output directly sent to the RMCK pin cannot be guaranteed. In such a case, set the frequency to one half or quarter of the PLL clock frequency (PRSEL [1:0]=00 or 10).
No.A1056-22/64
LC89058W-E
10.1.7 Output clocks (RMCK, RBCK, RLRCK, SBCK, SLRCK) * The LC89058W-E features two clock systems (R and S systems) in order to supply the various needed clocks to peripheral devices such as A/D converter and DSP. * The clock output settings for the R and S systems are done with PLLACC, PLLDV1, PLLVD2, PRSEL[1:0], XRSEL[1:0], XRBCK[1:0], XRLRCK[1:0], PSBCK[1:0], PSLRCK[1:0], XSBCK[1:0], and XSLRCK[1:0]. * Setting range for each clock output pin when the PLL is used as source (1) RMCK: Selection from 1/1, 1/2, and 1/4 of PLLACC, PLLDV0, PLLDV1, or 512fs (2) RBCK: 64fs output (3) RLRCK: fs output (4) SBCK: Selection from 128fs, 64fs, 32fs, and 16fs (5)SLRCK: Selection from 2fs, fs, 1/2fs, and 1/4fs * Setting range for each clock output pins when the XIN is used as source (1) RMCK: Selection from 1/1, 1/2, and 1/4 of 12.288MHz or 24.576MHz (2) RBCK: Selection from 12.288MHz, 6.144MHz, and 3.072MHz (3) SBCK: Selection from 12.288MHz, 6.144MHz, and 3.072MHz (4) RLRCK: Selection from 192kHz, 96kHz, and 48kHz (5) SLRCK: Selection from 192kHz, 96kHz, and 48kHz * The polarity of RMCK can be reversed with RMCKP. * The polarity of RBCK, RLRCK, SBCK, and SLRCK can be reversed with RBCKP, RLRCKP, SBCKP, and SLRCKP. Table 10.3 List of Output Clock Frequencies (Bold Items = Initial Settings)
Output Pin Name PLL Source (Internal VCO CK) 512fs 512fs RMCK 256fs 128fs RBCK 64fs XIN Source (XIN input CK) 12.288MHz 12.288MHz 6.144MHz 12.288MHz 6.144MHz 3.072MHz RLRCK fs 128fs SBCK 64fs 32fs 16fs 2fs SLRCK fs fs/2 fs/4 24.576MHz 24.576MHz 12.288MHz 6.144MHz (RMCK=24.576MHz) (RMCK12.288MHz) (RMCK6.144MHz)
192kHz 96kHz 48kHz 12.288MHz 6.144MHz 3.072MHz (RMCK=24.576MHz) (RMCK12.288MHz) (RMCK6.144MHz)
192kHz 96kHz 48kHz
Notes: * RBCK and SBCK output clock must not quicken more than RMCK output clock frequency. Also, RBCK and SBCK output clock are set to become 1/2 or less of RMCK output clock at XIN source. If it doesn't follow these conditions, RBCK and SBCK clocks are not output.
No.A1056-23/64
LC89058W-E
10.1.8 Output clocks block diagram (RMCK, RBCK, RLRCK, SBCK, SLRCK, XMCK) * The relationships between the output clock and switch function are shown below. * PLL in the figure indicates the PLL source and XIN the XIN source. * The contents in the quotation marks "" by the switch function blocks correspond to the write command names. * The broken lines connecting the switches indicate coordinated switching. * Lock/Unlock is switched automatically by PLL locking/unlocking.
"PLLDV0" "PLLDV1" 1/1 1/2 1/4 Input fs Lock / Unlock "OCKSEL" "EXTSEL"
Master Clock Generator PLL Source 512fs
512fs
Auto "PLLACC" PLL
X'tal Source 12.288MHz 24.576MHz
512fs 256fs 128fs Mute
"PRSEL[1:0]"
12.288MHz 24.576MHz
"XINSEL"
"RMCKP" "XRSEL[1:0]" 1/1 1/2 1/4 Mute
XIN "EMCKP" GPIO0
RMCK
"XMSEL[1:0]" 1/1 1/2 Mute
XMCK
64fs
PLL
"XRBCK[1:0]" 12.288MH 6.144MHz 3.072MHz Mute
XIN GPIO1 RBCK
fs
PLL
"XRLRCK[1:0]" 192kHz 96kHz 48kHz Mute
XIN GPIO2 RLRCK
"PSBCK[1:0]" 128fs 64fs 32fs 16fs
"SBCKP" PLL Master / Slave
"XSBCK[1:0]" 12.288MH 6.144MHz 3.072MHz Mute "PSLRCK[1:0]" 2fs fs fs/2 fs/4
SBCK
XIN
"SLRCKP" PLL
"XSLRCK[1:0]" 192kHz 96kHz 48kHz Mute
SLRCK
XIN
Figure 10.4 Clock Output Block Diagram
No.A1056-24/64
LC89058W-E
10.1.9 Output of clock switch transition signal (CKST) * CKST outputs pulse when the output clock changes by PLL lock/unlock. * The polarity of the CKST pulse output can be reversed with CKSTP. Subsequently, CKSTP is assumed to be 0. * In the lock-in stage, the CKST falls at the word clock generated from the XIN clock after PLL is locked following detection of input data, and rises at the same timing as RERR after a designated period. * In the unlock stage, the CKST falls at the same timing as RERR, PLL lock detection signal, and rises after word clocks generated from the XIN clock are counted for a designated period. * Change of the PLL lock status and timing of the clock change can be seen by detecting the rising and falling edges and pulses of CKST. * The clock is switched after the PLL lock condition is tested and identified. The timing of this clock switching is determined by setting the PTOXW [1:0]. The initial value is such that the clock is switched in 2.7ms after the falling edge of CKST. The value, however, assumes that the oscillation amplifier is set to permanent operation mode. If the oscillation amplifier is set to be stopped after PLL locking, the startup time before the oscillation amplifier stabilizes after PLL unlocking, is added. * A free-running clock is output from the clock output pin immediately after PLL unlocking.
RX0 to RX6 PLL status XIN clock PLL clock UNLOCK
Digital data LOCK
After PLL lock CKST RERR RMCK XIN clock (a): Lock-in stage (CKSTP=0)
3ms to 144ms
2.7ms
PLL clock
RX0 to RX6 PLL status XIN clock PLL clock
Digital data LOCK UNLOCK
Same timing as RERR CKST RERR RMCK PLL clock **: When set to PTOXW[1:0]=00 (max.) (b): Unlock stage (CKSTP=0)
5.3ms
2.7ms**
XIN clock
Figure 10.5 Clock Switch Timing
No.A1056-25/64
LC89058W-E
10.1.10 Output clocks generated when input S/PDIF reception is limited * The same processing performed when the PLL is unlocked is carried out if an S/PDIF input exceeding the reception range limit (which can be defined by FSLIM[1:0]) is supplied. The clock source is then switched to the XIN clock and clocks are output from respective clock pins.
DIN0-6 PLL status RERR RMCK RBCK RLRCK
fs=44.1kHz LOCK
fs=192kHz LOCK
fs=96kHz LOCK
PLL clock
PLL clock (a) When set to FSLIM[1:0]=00 (No limit on inputs) XIN clock
PLL clock
UNLOCK fs=96kHz LOCK
DIN0-6 PLL status RERR RMCK RBCK RLRCK
fs=44.1kHz LOCK
fs=192kHz LOCK
PLL clock
XIN clock
PLL clock
(b) When set to FSLIM[1:0]=01 (Receive frequency is limited to 96kHz or lower)
DIN0-6 PLL status RERR RMCK RBCK RLRCK
fs=44.1kHz LOCK
fs=192kHz LOCK
fs=96kHz LOCK
PLL clock
XIN clock
(c) When set to FSLIM[1:0]=10 (Receive frequency is limited to 48kHz or lower)
Figure 10.6 Output Clocks Generated When Input Data Reception Is Limited
No.A1056-26/64
LC89058W-E
10.2 S/PDIF I/O 10.2.1 Reception range of S/PDIF input * The guaranteed reception range of input data is shown below. Table 10.4: S/PDIF Reception Range (FSLIM [1:0]=00)
PLL Output Clock Setting 512fs Input Data Reception Range 30kHz to 192kHz
Note: (1) Reception range of RX1 is 32kHz to 96kHz. (2) PLL output clock is frequency-divided with PLLACC, PLLDIV and PRSEL [1:0] and is output from RMCK. * The fs reception range for input data can be limited within the set range of PLL output clocks stated above. This setting is carried out with FSLIM [1:0]. When this function is adopted, input data exceeding the set range is considered as an error, the clock source is automatically switched to the XIN source, and RDATA output data is subject to the RDTSEL setting. 10.2.2 S/PDIF I/O pins (RX0 to RX6, RXOUT1, RXOUT2) * S/PDIF input pins are 7 inputs at maximum. (1) RX1 is a coaxial-compatible input pin. When using RX1, connect RX0 and RX2 to GND. (2) RX0, RX2, RX3, RX4, RX5, and RX6 are TTL input level pins with 5V-tolerance voltage. (3) Make sure that the selected pins are not input-open. For points to notice on RX1, see the following subsection. (4) The unselected pins are pulled down with their internal resistors. * The demodulation input and S/PDIF through-output pins RXOUT1 and RXOUT2 data can be selected independently. (1) The demodulation data is selected with RISEL[2:0]. (2) The RXOUT1 output data is selected with ROSEL[2:0]. (3) The RXOUT2 output data is selected with RXSEL[2:0]. * It is possible to deselect all of RX0 to RX6 with RISEL[2:0] (RISEL[2:0]=111). * RXOUT1 and RXOUT2 can be muted with RXOSEL[2:0] and RXSEL[2:0], respectively. Muting is recommended to reduce jitter when RXOUT1 and RXOUT2 are not used. * The data input state can be monitored with the RXMON setting. The status of each data input pin is stored in CCB address 0xEA and output registers DO0 to DO7. Moreover, the latest information can be read with the microcontroller by setting the interrupt processing command INDET. For details, see Chapter 12, Microcontroller Interface. * The frequencies of input data that can be monitored with this setting is from 32kHz to 192kHz. The data detection function applies to IEC60958 compatible S/PDIF data. The frequency of the clock supplied to XIN when RXMON is set is limited to 24.576MHz. LC89058W-E does not run at any clock frequency other than 24.576MHz. Moreover, since this function uses the XIN clock, the oscillation amplifier must be set in the continuous operation mode when RXMON is set. * When the data input monitoring is specified, the input pins, except RX1pin and those which are selected for demodulation, are pulled down. This is to preclude input-open when detecting no connection input pins. For the peripheral circuit of the RX1 pin, see the following page.
No.A1056-27/64
LC89058W-E
10.2.3 S/PDIF input circuits (RX0 to RX6) * RX0, RX2, RX3, RX4, RX5, and RX6 can be received the data of 32kHz to 192kHz. * RX1 can be received up to 96kHz data. * If RX1 with a built-in amplifier is used as a coaxial input pin, malfunction may occur due to the influence from the adjacent RX0 and RX2 input pins. To avoid the influences from those pins, fix RX0 and RX2 to "L". In addition, the pull-down resistor is inserted after the coupling capacitor for the noise measures, when the signal is not connected with RX1 is selected. * When RX1 is selected and the input signal to RX1 is always fixed to either "H" or "L" (Toslink etc), RX0 and RX2 processes are not required. * RX0, RX2, RX3, RX4, RX5, and RX6 are TTL input level compatible S/PDIF input pins with 5V-tolerance voltage. LC89058W-E
RX0 Coaxial RX1 RX2
470k
RX3 RX4 Optical etc. RX5 RX6
(a) Coaxial input circuit
Optical RX0 RX1 RX2
LC89058W-E
RX3 RX4 Optical etc. RX5 RX6
(b) Optical input circuit
Figure 10.7 S/PDIF Input Circuits
No.A1056-28/64
LC89058W-E
10.3 Serial Audio Data I/O 10.3.1 Output data format (RDATA) * The output format is set with OFDSEL. * The initial value of output format is I2S. * Output data is output synchronized with the RLRCK edge immediately after the RERR output becomes "L".
L-ch RLRCK (O) RBCK (O) RDATA (O) MSB 24bit (0): I S data output
2
R-ch
LSB
MSB 24bit
LSB
L-ch RLRCK (O) RBCK (O) RDATA (O) MSB 24bit LSB MSB 24bit (1): MSB-first front-loading data output
R-ch
LSB
MSB
Figure 10.8 Data Output Timing
No.A1056-29/64
LC89058W-E
10.3.2 Serial audio data input format (SDIN) * LC89058W-E is provided with a serial data input pin of SDIN. * The format of the serial audio data input to SDIN and the demodulation data output format must be identical. * The initial value of modulation data output format is I2S. * The SDIN data to be input must be in synchronization with the RBCK and RLRCK clocks. * The data input from the SDIN pin is through-output to the RDATA pin. * The SDIN pin must be connected to GND when it is not used.
24bit SDIN (I) RLRCK (O) RBCK (O) RDATA (O) MSB LSB
2
24bit LSB MSB R-ch LSB
MSB L-ch
MSB
LSB
(0): I S data output
24bit SDIN (I) RLRCK (O) RBCK (O) RDATA (O) MSB LSB MSB MSB LSB L-ch MSB
24bit LSB R-ch MSB
LSB
MSB
(1): MSB-first front-loading data input
Figure 10.9 Serial Audio Data Input Timing
No.A1056-30/64
LC89058W-E
10.3.3 Output data switching (SDIN, RDATA) * RDATA outputs demodulation data when the PLL is locked, and outputs SDIN input data when the PLL is unlocked. This output is automatically switched according to the PLL locked/unlocked status. For details, see the timing charts below. * When SDIN input data is selected, switch to a clock source synchronized to the SDIN data. * With the RDTSTA setting, the SDIN input data is output to RDATA regardless of the locked/unlocked status of the PLL. * With the RDTMUT setting, the RDATA output data can be also muted forcibly. * Even when the clock source is set to XIN with OCKSEL and RCKSEL, the PLL continues operating as long as the PLL is not stopped with PLLOPR. At this time, the PLL status is continuously output from RERR unless error output is forcibly set with RESTA. Moreover, the processed information can be read with the microcontroller interface regardless of the PLL status.
PLL status CKST RERR RDATA CKSTP=0
UNLOCK
LOCK
SDIN data
Muted (a): Lock-in stage
Demodulation data
PLL status CKST RERR RDATA CKSTP=0
LOCK
UNLOCK
Demodulation data (b): Unlock stage
Muted
SDIN data
Figure 10.10 Timing Chart of RDATA Output Data Switching
No.A1056-31/64
LC89058W-E
10.3.4 Data block diagram (RX0 to RX6, RXOUT1, RXOUT2, RDATA, SDIN) * Select the demodulated data and the SDIN input data with RDTSEL and RDTSTA, and mute processing can be performed with RDTMUT. * Moreover, GPIO0 input data can be selected with EXTSEL. Also, GPIO0 can be subject to mute processing with EDTMUT. See Chapter 11 for the selector function for the general-purpose I/O pins (GPIO0 to GP1O3).
RX0 RX1 RX2 RX3 RX4 RX5 RX6
MUX
"ROSEL[2:0]"
S/PDIF
"ROSEL[2:0]=111" RXOUT1
"RXSEL[2:0]"
S/PDIF
"RXSEL[2:0]=111" RXOUT2
"RISEL[2:0]" DIR
"RDTSEL" "RDTSTA" "RDTMUT" "EXTSEL" RDATA
SDIN GPIO3 "EDTMUT"
Figure 10.11 Data System Diagram 10.3.5 Calculation of input data sampling frequency (MOUT) * The input data sampling frequency is calculated using the XIN clock. * In the mode where the oscillation amplifier automatically stops according to the lock status of the PLL, the input data sampling frequency is calculated during the RERR error period and completed when the oscillation amplifier stops with holding the value. Therefore, the value remains unchanged until the PLL becomes unlocked. * If the oscillation amplifier is in a continuous operation mode, calculation is repeated constantly. Even if sampling changes within the PLL capture range for input data whose channel status sampling information does not change, the calculation results that follow the input data can be read. * The calculation results can be readout via MOUT pin or with the microcontroller interface. Since the MOUT pin is also used to generate the emphasis information, set the contents of the MOUT pin output by MOSEL. The fs calculation output to the MOUT pin is limited. The FSSEL[1:0] sets the contents of the MOUT pin output. Table 10.5: MOUT Pin Output Mode Settings
FSSEL1 0 0 1 1 FSSEL0 0 1 0 1 MOUT Pin H Output Conditions When calculating 32kHz, 44.1kHz or 48kHz When calculating 88.2kHz or 96kHz When calculating 176.4kHz or 192kHz When calculating 88.2kHz, 96kHz or higher
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10.4 Error Output Processing 10.4.1 Lock error and data error output (RERR) * RERR outputs an error flag when a PLL lock error or a data error occurs. * It is possible to treat non-PCM data reception as an error by the RESEL setting. * The RERR output conditions are set with RESTA. Since the PLL status can be output at all times, the PLL status can be always monitored, even when the clock source is XIN. 10.4.2 PLL lock error * The PLL gets unlocked for input data that lost bi-phase modulation regularity, or input data for which preambles B, M, and W cannot be detected. However, even if preambles B, M, and W are detected if the timing does not conform to the IEC60958, the PLL get unlocked and processed. For example, period of preamble B is not every192 frames. * RERR turns to "H" when the PLL lock error occurs and returns to "L" when the data demodulation returns normal and "H" is held for somewhere between 3ms to 144ms. This holding time is determined with the ERWT[1:0] setting. * The rising and falling edges of RERR are synchronized with RLRCK. 10.4.3 Input data parity error * Odd number of errors among parity bits in input data and input parity errors are detected. * If an input parity error occurs 9 or more times in succession, RERR turns to "H" indicating that the PLL is locked, and after holding "H" for somewhere between 3ms and 144ms, it returns to "L". * The error flag output format can be selected with REDER, when an input parity error is output less than 8 times in succession. 10.4.4 Other errors * Even if RERR turns to "L", the channel status bits of 24 to 27 (sampling frequency) are always fetched and the data of the previous block is compared with the current data. Moreover, the input data sampling frequency is calculated from the fs clock extracted from the input data, and the fs calculated value is compared in a same way as described above. If any difference is detected in these data, RERR is instantly made "H" and the same processing as for PLL lock errors is carried out. * The PLL causes a lock error when the fs changes as described above. However, in order to support sources with a variable fs (for example a CD player with a variable pitch function), it is possible to set with FSERR not to output an error flag unless fs changes exceeding the PLL capture range. In the FSERR setting, when the PLL is locked, RERR is turned to "L" without reflecting the fs calculation result to the error flag concerning input data within reception range by FSLIM [1:0]. Moreover, the data comparison at the channel status bits of 24 to 27 as described above is not performed. * If a setting which regard non-PCM data input as an error is made with RESEL, RERR turns to "H" when non-PCM data input is detected. At this time, the PLL locked status and various output clocks are subject to the input data, but the output data is muted.
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10.4.5 Data processing upon occurrence of errors (lock error, parity error) * The data processing upon occurrence of an error is described below. If 8 or fewer input parity errors occur in succession and transfer data is PCM audio data, the data is replaced by the one saved each in L-ch and R-ch in the previous frame. However, if the transfer data is non-PCM data, the error data is output as it is. * Non-PCM data is the data of when bit 1 (audio sample word) of the channel status turns to "H" based on the data detected prior to the occurrence of the input parity error. * Output data is muted when a PLL lock error occurs or a parity error occurs 9 or more times in succession. * As for the channel status output, the data of the previous block is held in 1-bit units when a parity error occur 8 or fewer times in succession. Table 10.6 Data Processing upon Error Occurrence
Data Demodulation data fs calculation result Channel status PLL Lock Error "L" "L" "L" Input Parity Error (a) "L" Output "L" Input Parity Error (b) Previous value data Output Previous value data Input Parity Error (c) Output Output Previous value data
* Input parity error (a): If occurs 9 or more times in succession * Input parity error (b): If occurs 8 or fewer times in succession, in case of audio data * Input parity error (c): If occurs 8 or fewer times in succession, in case of non-PCM burst data
1occurrence Input data
L-1
R-1
L-2
R-2
L-3
R-3
L-4
R-4
L-5
R-5
L-6
R-6
L-7
R-7
L-8
R-8
RERR
RLRCK
RDATA
L-0
R-0
L-1
R-0
L-2
R-2
L-2
R-2
L-2
R-2
L-2
R-2
L-2
R-ch Previous value data
L-ch R-ch Previous value data
9 times or more: Muting
Figure 10.12 Example of Data Processing upon Parity Error Occurrence
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10.4.6 Processing during error recovery * When preambles B, M, and W are detected, PLL becomes locked and data demodulation begins. * Demodulation data is output from the RLRCK edge after RERR turns to "L".
RERR Lock Signal RLRCK RDATA 3ms to 144ms OK
Data
Output start from RWCK edge immediately after RERR is lowered
Figure 10.13 Data Processing When Data Demodulation Starts
________
10.5 Data Delimiter Bit 1 Output ( AUDIO ) ____________ * AUDIO outputs the channel status data delimiter bit 1 information. * Outputs bit 1 of the channel status that indicates whether the input bi-phase data is PCM audio data. ____________ AUDIO is immediately output upon detection of RERR even during "H" output period. * OR-output with IEC61937 or with the DTS-CD/LD detection flag is also possible with AOSEL.
____________
______ AUDIO L H
Table 10.7 AUDIO Output
Output Conditions PCM audio data (CS bit 1 = "L") Non-audio data (CS bit 1 = "H")
10.6 Emphasis Information Output (EMPHA) * MOUT can output whether there is 50/15s emphasis parameter for consumer by switching the contents of MOUT output by MOSEL. * MOUT is immediately output upon detection of RERR even during "H" output. Table 10.8 MOUT Output
MOUT L H Output Conditions No pre-emphasis 50/15s pre-emphasis
10.7 IEC61937, DTS-CD/LD Detection Flag Output * A function to output IEC61937 and DTS-CD/LD detection flag for non-PCM data is provided. * DTS-CD/LD is compatible with "14-bit format." * When bit 1 of channel status is non-PCM data, the IEC61937 sync signal is detected and detection flag is output. If bit 1 is PCM data, detection flag is not output. * The DTS-CD/LD sync signal detection is done based on the sync pattern and the base frequency. The sync pattern is checked every 4096th frame, and the detection status is held until the sync pattern is no longer verified. *The IEC61937 and DTS-CD/LD detection flags can be readout with the microcontroller interface in addition to output ____________ to the AUDIO pin by AOSEL. When the UNPCM non-PCM signal output setting is selected through the INT output contents setting, an interrupt signal is output from INT detecting an IEC61937 or DTS-CD/LD sync signal. Reading output register from this information can see details of Non-PCM signal. This information is used to read out the output register and identify the details of the non-PCM signal * The detection flags are cleared when fs is changed or when a PLL lock error or data error occurs.
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11 Description of General-purpose I/O Function (GPIO0, GPIO1, GPIO2, GPIO3)
11.1 Initial Settings * When setting general-purpose I/Os for input, pull down INT with a 10k resistors. When settings general-purpose I/Os for output, pull up INT with a 10k resistor. See Chapter 9 for INT pin settings. * If general-purpose I/Os are set to the output pin, the serial data input from the microcontroller interface is converted to parallel data and output from of GPIO0, GPIO1, GPIO2, and GPIO3. * If general-purpose I/Os are set to the input pin, select one of the functions listed below with GPIOS. (1) Store the parallel data input from the GPIO0, GPIO1, GPIO2, and GPIO3 in the internal register and readout the contents of that register through the microcontroller interface (GPIOS=0). (2) Configure a 2-to-1 (4 bits wide) selector that selects either the audio format data and clock that are input to the GPIO0, GPIO1, GPIO2, and GPIO3 pins, or data and clock demodulated by the DIR block. RMCK, RBCK, RLRCK, and RDATA are the outputs from the selector (GPIOS=1). 11.2 Output Function * The data output directed to the GPIO0, GPIO1, GPIO2, and GPIO3 are stored at CCB address 0xE8, command address 10, input register bits DI12 to DI15, or register PI[3:0]. * The data stored in PI[3:0] are transmitted out of the GPIO0, GPIO1, GPIO2, and GPIO3 pins. 11.3 Input Function 11.3.1 GPIOS=0 * The data input to the GPIO0, GPIO1, GPIO2, and GPIO3 are taken into CCB address 0xEB, output register bits DO0 to DO3, or register PO[3:0]. * The data must be readout by setting the interrupt source GPIO to INT or at an arbitrary timing. The way in which the data is taken into the register depends on how it is readout. 11.3.1.1 GPIO=1 (using INT ) (1) XIN must always be given the specified clock and set in continuous operating mode (default). (2) The data inputs to the GPIO0, GPIO1, GPIO2, and GPIO3 are taken into the register on a 24kHz clock. (3) When the state of one of the data inputs changes, INT turns to "L" and suspends the data transfer to the register. (4) The interrupt sources for CCB address 0xEA, output register DO14, and register OGPIO must be verified. (5) INT turns "H" and the data is held in the register immediately when address 0xEA is readout. (6) The read data from the PO[3:0] is transferred to the microcontroller. At the same time, the data in the register is cleared. (7) The contents of the register are updated if INT turns to "L" before P0[3:0] is readout. 11.3.1.2 GPIO=0 (not using INT ) (1) The data inputs to the GPIO0, GPIO1, GPIO2, and GPIO3 pins are taken in when the CCB address 0xEB is set. (2) The data read from the PO[3:0] is transferred to the microcontroller. At the same time, the data in the register is cleared.
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11.3.2 GPIOS=1 * The figure below shows the relationship between GPIO0, GPIO1, GPIO2, GPIO3 which are input to the selector and the DIR block signal, and RMCK, RBCK, RLRCK, RDATA which are output from the selector and the control signal.
4 ADC
24
Lock judgment 4 "EXTSEL" 4 4 RMCK RBCK RLRCK RDATA
16 17 20 21
SDIN DIR XIN-MCK XIN-BCK XIN-LRCK PLL-MCK PLL-BCK PLL-LRCK PLL-DATA "EMCKP" 4
XM radio
44 45 46 47
GPIO0 GPIO1 GPIO2 GPIO3 "EDTMUT"
Figure 11.1 Selector Configuration Diagram Table 11.1 Selector I/O Signals
Input Pin or Input Signal EXTSEL=1 PLL Lock State GPIO0 (pin 44) GPIO1 (pin 45) GPIO2 (pin 46) GPIO3 (pin 47) PLL-MCK PLL-BCK PLL-LRCK PLL-DATA EXTSEL=0 PLL Unlock State XIN-MCK XIN-BCK XIN-LRCK SDIN RMCK (pin 16) RBCK (pin 17) RLRCK (pin 20) RDATA (pin 21) Output pin
Note: The selector output generated when the PLL is locked can be changed to the XIN clock system by setting the OCKSEL and RCSEL. * EXTSEL is enabled by setting GPIOS=1. When GPIOS=0 is set, the state of EXTSEL=0 is output from each pin. * The clock input to GPIO0 can be inverted by EMCKP and sent to RMCK. * The data to be input to GPIO3 must conform to the PLL-DATA or SDIN audio format. * The data input to GPIO3 can be muted by EDTMUT. * EMCKP and EDTMUT are enabled when GPIOS=1 is set. * The above settings are valid only when the master mode is set and must not be set when the slave mode is set.
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_____
12. Microcontroller Interface ( INT , CL, CE, DI, DO)
12.1 Description of Microcontroller Interface ____ 12.1.1 Interrupt output ( INT) * Interrupts is output when a change has occurred in the PLL lock status or output data information. ______ * Interrupt output consists of the register for selecting the interrupt source, the INT pin that outputs that state transition, and the registers that store the interrupt source data. ______ * Normally INT is held "H" and output "L" upon occurrence of an interrupt. Following "L" output, it is cleared and returns to "H" immediately when the interrupt source output register is readout. * The interrupt sources can be selected among the following items. Multiple sources can be selected at the same time ______ with the contents of CCB address 0xE8 and command address 8. INT outputs OR calculation result of the selected interrupt sources. INT output = (selected source 1) + (selected source 2) + ... + (selected source n) Table 12.1 Interrupt Source Setting Contents
No. 1 2 3 4 5 6 7 8 Command Name ERROR INDET FSCHG CSRNW UNPCM PCRNW GPIO EMPF Output when RERR pin status has changed Output when input data pin status has changed (subject to oscillation amplifier operation condition) Output when input fs calculation result has changed. (subject to oscillation amplifier condition) Output when channel status data of first 48 bits have updated ______ Output when AUDIO pin status has changed Output when burst preamble Pc has been updated Output when the state of input data changes when the general-purpose I/O parallel input is set. Output when emphasis information has changed Description
______
* The contents of set interrupt source are saved in output registers DO8 to DO15 of CCB address 0xEA, when the ____________ source occurs. However, for the read registers for source items 1 and 5, the each status of the RERR and AUDIO pins are output at the time of reading. Other data except for source items 1 and 5 are saved in the registers upon occurrence of an interrupt source. * Concerning source items 2 and 3, the oscillation amplifier clock is used. Therefore, if the status is monitored even while the______ is locked, the oscillation amplifier must be set to the continuous operation mode. PLL * Clearing INT at the same time of readout of an output register is carried out immediately after the output register ______ 0xEA is set. However, INT is not cleared other than the 0xEA setting.
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12.1.2 CCB interface * The CCB interface is a SANYO's original serial bus format based on LSB-first communication, but three-state is employed instead of open-drain for the data output format of LC89058W-E. * Data input/output is performed following CCB address input. The same CCB address cannot be used for both read and write operation. Table 12.2 Relationship between Register I/O Contents and CCB Addresses
Register I/O contents Function setting data input Input detection, interrupt output fs data output CS data output Pc data output R/W Write Read Read Read Read CCB address 0xE8 0xEA 0xEB 0xEC 0xED B0 0 0 1 0 1 B1 0 1 1 0 0 B2 0 0 0 1 1 B3 1 1 1 1 1 A0 0 0 0 0 0 A1 1 1 1 1 1 A2 1 1 1 1 1 A3 1 1 1 1 1
12.1.3 Data write procedure * Input is performed in the following sequence: CCB addresses of A0 to A3 and B0 to B3, chip addresses of DI0 and DI1, command addresses of DI4 to DI7, and data of DI8 to DI15. DI2 and DI3 are reserved for the system. So, DI2 and DI3 input must be doing "0". * For the chip addresses, DI0 corresponds to CAL (low-order), and DI1 to CAU (high-order). For details, see section 9.2. 12.1.4 Data read procedure * Read data is output from DO. DO is in the high impedance state when CE is "L", and begins outputting from the rising edge of CE after output setting is established at the CCB address. DO then returns to the high impedance state at the falling edge of CE. * If DO outputs are shared using multiple LC89058W-E units, it is possible to set the DO outputs of the LC89058W-E units of which data is not to be read to be always in the high impedance state with DOEN. With this setting, only the targeted outputs can be read. 12.1.5 Points to notices when normal H clock is used * The CCB interface uses CL of a normal L clock, and it is also possible to use CL of a normal H clock. However, input the clock based on CCB microcontroller interface AC characteristics. * CL is lowered before CE is raised when data reads.
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12.1.6 I/O timing
CE CL DI DO
B0 B1 B2 B3 A0 A1 A2 A3 CAL CAU DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI9 DI10 DI1 DI2
DI15
Hi-Z
Figure 12.1 Input Timing Chart (Normal L clock)
CE CL DI DO
B0 B1 B2 B3 A0 A1 A2 A3 CAL CAU DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI9 DI10 DI11 DI12
DI15
Hi-Z
Figure 12.2 Input Timing Chart (Normal H clock) (CL need not be lowered before CE is raised.)
CE CL DI DO
B0 B1 B2 B3 A0 A1 A2 A3
Hi-Z
DO0
DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8

DOn
Figure 12.3 Output Timing Chart (Normal L clock)
CE CL DI DO
B0 B1 B2 B3 A0 A1 A2 A3
Hi-Z
DO0
DO1 DO2 DO3 DO4 DO5 DO6 DO7

DOn
Figure 12.4 Output Timing Chart (Normal H clock) (CL is lowered before CE is raised, and DO0 need be read with port)
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12.2 Write Data 12.2.1 List of write commands * A list of the write commands is shown below. * To write the commands shown in the following table, set the CCB address to 0xE8. Table 12.3 Write Register Map
Add. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Setting Items System setting 1 System setting 2 Master clock R system output clock S system output clock Source switch Data I/O 1 Output format ___ INTsource selection RERR condition setting General-purpose I/O TEST System setting 3 Data I/O 2 PLL clock TEST DI15 TESTM 0 AMPOPR1 XRLRCK1 XSLRCK1 0 0 SLRCKP EMPF ERWT1 PI3 0 0 0 FSSEL1 0 DI14 0 0 AMPOPR0 XRLRCK0 XSLRCK0 RDTMUT ROSEL2 SBCKP GPIO ERWT0 PI2 0 0 RXSEL2 FSSEL0 0 DI13 0 FSLIM1 0 XRBCK1 XSBCK1 RDTSTA ROSEL1 RLRCKP PCRNW FSERR PI1 0 CKSTP RXSEL1 0 0 DI12 0 FSLIM0 PLLOPR XRBCK0 XSBCK0 RDTSEL ROSEL0 RBCKP UNPCM RESTA PI0 0 RMCKP RXSEL0 0 0 DI11 0 RXMON XMSEL1 XRSEL1 PSLRCK1 0 0 0 CSRNW 0 0 0 0 EDTMUT PTOXW1 0 DI10 0 AOSEL XMSEL0 XRSEL0 PSLRCK0 0 RISEL2 0 FSCHG 0 0 0 PLLDV1 EMCKP PTOXW0 0 DI9 DOEN 0 XINSEL PRSEL1 PSBCK1 OCKSEL RISEL1 0 INDET REDER 0 0 PLLDV0 EXTSEL 0 0 DI8 SYSRST MOSEL 0 PRSEL0 PSBCK0 0 RISEL0 OFDSEL ERROR RESEL 0 0 PLLACC GPIOS 0 0
Addr: Command address * The shaded parts of DI8 to DI15 in the command area are reserved bits. Input must be doing "0". * Command addresses 11 and 15 are reserved for testing purposes. Writing to these addresses is prohibited.
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12.2.2 Details of write commands CCB address: 0xE8; Command address: 0; System setting 1
DI7 0 DI6 0 DI5 0 DI4 0 DI3 0 DI2 0 DI1 CAU DI0 CAL
DI15 TESTM
DI14 0
DI13 0
DI12 0
DI11 0
DI10 0
DI9 DOEN
DI8 SYSRST
SYSRST
System reset 0: Don't reset (initial value) 1: Reset circuits other than command registers DO pin output setting 0: Output (initial value) 1: Always high impedance state (read disabled) Test mode setting 0: Normal operation (initial value) 1: Enter test mode
DOEN
TESTM
* When reset by SYSRST is performed, RBCK outputs "L" and BLRCK outputs "H."
CCB address: 0xE8; Command address: 1; System setting 2
DI7 0 DI6 0 DI5 0 DI4 1 DI3 0 DI2 0 DI1 CAU DI0 CAL
DI15 0
DI14 0
DI13 FSLIM1
DI12 FSLIM0
DI11 RXMON
DI10 AOSEL
DI9 0
DI8 MOSEL
MOSEL
MOUT output contents setting 0: Output channel status emphasis information (initial value) 1: Output input data fs calculation results (output conditions are given by FSSEL[1:0].)
AUDIO output mode 0: Only output channel status bit 1 (initial value) 1: Output channel status bit 1, IEC61937 or DTS-CD/LD detection flag
AOSEL
RXMON
Setting digital audio data (S/PDIF) input status monitoring 0: Don't monitor S/PDIF input status (initial value). 1: Monitor S/PDIF input status Setting of sampling frequency reception range for input digital signal 00: No limit (initial value) 01: fs96kHz (when exceeded, data is muted and clock is set to XIN system output) 10: fs48kHz (when exceeded, data is muted and clock is set to XIN system output) 11: Reserved
FSLIM[1:0]
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CCB address: 0xE8; Command address: 2; Master clock setting
DI7 0 DI6 0 DI5 1 DI4 0 DI3 0 DI2 0 DI1 CAU DI0 CAL
DI15 AMPOPR1
DI14 AMPOPR0
DI13 0
DI12 PLLOPR
DI11 XMSEL1
DI10 XMSEL0
DI9 XINSEL
DI8 0
XINSEL
XIN input frequency setting 0: 12.288MHz (initial value) 1: 24.576MHz XMCK output frequency setting 00: 1/1 of XIN input frequency (initial value) 01: 1/2 of XIN input frequency 10: 1/4 of XIN input frequency 11: Muted PLL (VCO) operation setting 0: Operate (initial value) 1: Stop Oscillation amplifier operation setting 00: Permanent continuous operation (initial value) 01: Reserved 10: Automatic stopping of oscillation amplifier while PLL is locked 11: Stop
XMSEL [1:0]
PLLOPR
AMPOPR [1:0]
* In order to replace LC89057W-VF4A-E, setting contents of the AMPOPR[1:0] are different from those of LC89057W-VF4A-E.
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LC89058W-E
CCB address: 0xE8; Command address: 3; R system output clock setting
DI7 0 DI6 0 DI5 1 DI4 1 DI3 0 DI2 0 DI1 CAU DI0 CAL
DI15 XRLRCK1
DI14 XRLRCK0
DI13 XRBCK1
DI12 XRBCK0
DI11 XRSEL1
DI10 XRSEL0
DI9 PRSEL1
DI8 PRSEL0
PRSEL [1:0]
Setting of RMCK output frequency while PLL is locked (enabled when PLLACC is set to "0") 00: 512fsx1/2 (256fs) (initial value) 01: 512fsx1/1 (512fs) 10: 512fsx1/4 (128fs) 11: Muted Setting of RMCK output frequency during XIN source 00: 1/1 of XIN input frequency (initial value) 01: 1/2 of XIN input frequency 10: 1/4 of XIN input frequency 11: Muted Setting of RBCK output frequency during XIN source 00: 3.072MHz output (RMCK6.144MHz) (initial value) 01: 6.144MHz output (RMCK12.288MHz) 10: 12.288MHz output (RMCK=24.576MHz) 11: Muted Setting of RLRCK output frequency during XIN source 00: 48kHz output (initial value) 01: 96kHz output 10: 192kHz output 11: Muted
XRSEL [1:0]
XRBCK [1:0]
XRLRCK [1:0]
* Don't do the setting to which RMCK=3.072MHz is output by XRSEL [1:0]=10(1/4 output) setting when XIN=12.288MHz is input because it doesn't satisfy the output setting condition of RBCK and SBCK. * Setting of XRBCK [1:0] relate to setting of RMCK output clock. RBCK output clock is set to become 1/2 or less of RMCK output clock at XIN source.
No.A1056-44/64
LC89058W-E
CCB address: 0xE8; Command address: 4; S system output clock setting
DI7 0 DI6 1 DI5 0 DI4 0 DI3 0 DI2 0 DI1 CAU DI0 CAL
DI15 XSLRCK1
DI14 XSLRCK0
DI13 XSBCK1
DI12 XSBCK0
DI11 PSLRCK1
DI10 PSLRCK0
DI9 PSBCK1
DI8 PSBCK0
PSBCK [1:0]
Setting of SBCK frequency while PLL is locked 00: 64fs output (initial value) 01: 128fs output 10: 32fs output 11: 16fs output Setting of SLRCK frequency while PLL is locked 00: fs output (initial value) 01: 2fs output 10: fs/2 output 11: fs/4 output Setting of SBCK frequency during XIN source 00: 3.072MHz output (RMCK6.144MHz) (initial value) 01: 6.144MHz output (RMCK12.288MHz) 10: 12.288MHz output (RMCK=24.576MHz) 11: Muted
PSLRCK [1:0]
XSBCK [1:0]
XSLRCK [1:0] SLRCK output frequency setting during XIN source 00: 48kHz output (initial value) 01: 96kHz output 10: 192kHz output 11: Muted * Setting of XSBCK [1:0] relate to setting of RMCK output clock. SBCK output clock is set to become 1/2 or less of RMCK output clock at XIN source.
No.A1056-45/64
LC89058W-E
CCB address: 0xE8; Command address: 5; Clock source switching; RDATA output setting
DI7 0 DI6 1 DI5 0 DI4 1 DI3 0 DI2 0 DI1 CAU DI0 CAL
DI15 0
DI14 RDTMUT
DI13 RDTSTA
DI12 RDTSEL
DI11 0
DI10 0
DI9 OCKSEL
DI8 0
OCKSEL
Clock source setting 0: Use XIN clock as source while PLL is unlocked (initial value) 1: Use XIN clock as source regardless of PLL status RDATA output setting while PLL is unlocked 0: Output SDIN data while PLL is unlocked (initial value) 1: Mute while PLL is unlocked RDATA output setting 0: According to RDTSEL (initial value) 1: Output SDIN input data regardless of PLL status RDATA mute setting 0: Output data selected with RDTSEL (initial value) 1: Muted
RDTSEL
RDTSTA
RDTMUT
* When the oscillation amplifier is set to the permanent continuous operation mode with AMPOPR [1:0] or fs changes are set not to be reflected to the error flag with FSERR, OCKSEL can switch the clock source while maintaining the RERR status. * The phase of R system clock and S system clock synchronize. * To input data to SDIN, select a clock synchronized with the SDIN input data. * The XIN source can be switched while maintaining the PLL locked status. However, since switching between clock and data output can be set independently; it is recommended to select mute or SDIN data for the output data when XIN source is switched. * If the oscillation amplifier is set to stop automatically when the PLL gets locked, XIN source switching from the PLL locked status disables the clock output. Be sure to set the oscillation amplifier to the continuous operation mode when switching the clock source to the XIN source.
No.A1056-46/64
LC89058W-E
CCB address: 0xE8; Command address: 6; Data I/O setting 1
DI7 0 DI6 1 DI5 1 DI4 0 DI3 0 DI2 0 DI1 CAU DI0 CAL
DI15 0
DI14 ROSEL2
DI13 ROSEL1
DI12 ROSEL0
DI11 0
DI10 RISEL2
DI9 RISEL1
DI8 RISEL0
RISEL [2:0]
Data demodulation input pin setting 000: RX0 selection (initial value) 001: RX1 selection 010: RX2 selection 011: RX3 selection 100: RX4 selection 101: RX5 selection 110: RX6 selection 111: None are selected (all inputs are connected to GND through pull-down resistors.) RXOUT1 output data setting 000: RX0 input data (initial value) 001: RX1 input data 010: RX2 input data 011: RX3 input data 100: RX4 input data 101: RX5 input data 110: RX6 input data 111: "L" fixed output
ROSEL [2:0]
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LC89058W-E
CCB address; 0xE8; Command address: 7; Data output format setting
DI7 0 DI6 1 DI5 1 DI4 1 DI3 0 DI2 0 DI1 CAU DI0 CAL
DI15 SLRCKP
DI14 SBCKP
DI13 RLRCKP
DI12 RBCKP
DI11 0
DI10 0
DI9 0
DI8 OFDSEL
OFSEL
Audio data output format setting 0: I2S data output (initial value) 1: 24 bits, MSB first, left-justification output RBCK output polarity setting 0: Falling RDATA data change (initial value) 1: Rising RDATA data change RLRCK output polarity setting 0: "L" period: L-channel data; "H" period: R-channel data (initial value) 1: "L" period: R-channel data; "H" period: L-channel data SBCK output polarity setting 0: Falling RDATA data change (initial value) 1: Rising RDATA data change SLRCK output polarity setting 0: "L" period: L-channel data; "H" period: R-channel data (initial value) 1: "L" period: R-channel data; "H" period: L-channel data
RBCKP
RLRCKP
SBCKP
SLRCKP
No.A1056-48/64
LC89058W-E
______
CCB address: 0xE8; Command address: 8; INT output contents setting
DI7 1 DI6 0 DI5 0 DI4 0 DI3 0 DI2 0 DI1 CAU DI0 CAL
DI15 EMPF
DI14 GPIO
DI13 PCRNW
DI12 UNPCM
DI11 CSRNW
DI10 FSCHG
DI9 INDET
DI8 ERROR
ERROR
RERR signal output setting 0: Don't output (initial value) 1: Output RERR pin status change Input data detection output setting 0: Don't output (initial value) 1: Output input data pin status change Setting of updated flag output of PLL lock frequency calculation result 0: Don't output (initial value) 1: Output updated flag of PLL lock frequency calculation result Output setting for updated flag of first 48-bit channel status data 0: Don't output (initial value) 1: Output update flag of first 48-bit channel status data Output setting for change flag of non-PCM data detection 0: Don't output (initial value) ____________ 1: Output AUDIO pin status change Output setting for updated flag of burst preamble Pc 0: Don't output (initial value) 1: Output updated flag of burst preamble Pc Input data updated flag output setting when general-purpose I/O parallel input is set (GPIOS=0) 0: Don't output (initial value) 1: Output input data updated flag Output setting of emphasis detection flag 0: Don't output (initial value) 1: Output emphasis detection flag
INDET
FSCHG
CSRNW
UNPCM
PCRNW
GPIO
EMPF
* The input data detection output setting functions when INDET=1 is set with the clock of 24.576MHz is supplied to the terminal XIN (XINSEL=1) and digital data input state monitoring function (RXMON=1) made effective. * The channel status update flag compares the first 48 bits of data of the previous block with those of the current block. If these data are identical, it outputs a flag, considering the data has been updated. * The burst preamble Pc update flag also compares the 16 bits of data of the previous block with those of the current data. If they are identical, an update flag is output. * The 4-bit input data updated flag when the general-purpose I/O parallel input is set, is output only when a change has occurred in the sampling data with a clock of 24kHz.
No.A1056-49/64
LC89058W-E
CCB address: 0xE8, Command address: 9; RERR output setting
DI7 1 DI6 0 DI5 0 DI4 1 DI3 0 DI2 0 DI1 CAU DI0 CAL
DI15 ERWT1
DI14 ERWT0
DI13 FSERR
DI12 RESTA
DI11 0
DI10 0
DI9 REDER
DI8 RESEL
RESEL
RERR output contents setting 0: PLL lock error or data error (initial value) 1: PLL lock error or data error or non-PCM data Setting of parity error flag output within 8 times in a row 0: Output only when non-PCM data is recognized (initial value) 1: Output only during sub-frame for which error was generated RERR output condition setting 0: Output PLL status all the time (Output PLL status even during XIN source) (initial status) 1: Forcibly output error (Set "H" to RERR forcibly) Setting of error flag output condition according to fs change 0: Reflect fs changes to error flag (initial value) 1: Don't reflect fs changes to error flag Setting of RERR wait time after PLL is locked 00: Cancel error after preamble B is counted 3 (initial value) 01: Cancel error after preamble B is counted 24 10: Cancel error after preamble B is counted 12 11: Cancel error after preamble B is counted 6
_________
REDER
RESTA
FSERR
ERWT [1:0]
* Non-PCM data is identical to the detection data output to AUDIO. * Output data is muted if an error occurs due to non-PCM data with RESEL. * The RESTA setting is not reflected to the output pins of data and clock. * For FSERR, the fs calculation result obtained while the oscillation amplifier is stopped is not reflected. In this case, fs changes consist of only channel status fs information. * ERWT[1:0] defines the interval of time for RERR to output error cancellation ("L") after PLL is locked. Since demodulated audio data is output after RERR cancels an error, you need to change this setting if the situation that the head of data is missing is a problem.
No.A1056-50/64
LC89058W-E
CCB address: 0xE8; Command address: 10; General-purpose I/O function
DI7 1 DI6 0 DI5 1 DI4 0 DI3 0 DI2 0 DI1 CAU DI0 CAL
DI15 PI3
DI14 PI2
DI13 PI1
DI12 PI0
DI11 0
DI10 0
DI9 0
DI8 0
PI0
Contents of data output to the GPIO0 pin when the general-purpose I/O parallel output is set 0: L (initial value) 1: H Contents of data output to the GPIO1 pin when the general-purpose I/O parallel output is set 0: L (initial value) 1: H Contents of data output to the GPIO2 pin when the general-purpose I/O parallel output is set 0: L (initial value) 1: H Contents of data output to the GPIO3 pin when the general-purpose I/O parallel output is set 0: L (initial value) 1: H
PI1
PI2
PI3
No.A1056-51/64
LC89058W-E
CCB address: 0xE8; Command address: 11; System settings 3
DI7 1 DI6 1 DI5 0 DI4 0 DI3 0 DI2 0 DI1 CAU DI0 CAL
DI15 0
DI14 0
DI13 CKSTP
DI12 RMCKP
DI11 0
DI10 PLLDV1
DI9 PLLDV0
DI8 PLLACC
PLLACC
PLL clock lock frequency setting 0: Manual setting (initial value) 1: Automatic control (see 10.1.6.) Set the PLL clock generated when 32kHz, 44.1kHz or 48kHz is received with PLLACC=1 0: 512fs output (initial value) 1: 256fs output Set the PLL clock generated when 88.2kHz or 96kHz is received with PLLAC=1 0: 256fs output (initial value) 1: 512fs output DIR block RMCK output setting 0: Normal output (initial value) 1: Inverted output CKST output polarity setting 0: Normal high output (initial value) 1: Normal low output
PLLDV0
PLLDV1
RMCKP
CKSTP
No.A1056-52/64
LC89058W-E
CCB address: 0xE8; Command address: 12; Data I/O setting 2
DI7 1 DI6 1 DI5 0 DI4 1 DI3 0 DI2 0 DI1 CAU DI0 CAL
DI15 0
DI14 RXSEL2
DI13 RXSEL1
DI12 RXSEL0
DI11 EDTMUT
DI10 EMCKP
DI9 EXTSEL
DI8 GPIOS
GPIOS
Setting of pins 44 to 47 input function (when INT pull-down is set) 0: General-purpose I/O parallel input (initial value) I: Selector input RMCK, RBCK, RLRCK, and RDATA output setting 0: Output data and clock of DIR function (initial value). 1: Output input signals to GPIO0, GPIO1, GPIO2, GPIO3 (GPIOS=1) GPIO0 output polarity setting (GPIOS=1) 0: Normal output (Initial value) 1: Inverted output GPIO3 mute setting (GPIOS=1) 0: Normal output (initial value) 1: Muted RXOUT2 output data setting 000: "L" fixed output (initial value) 001: RX0 input data 010: RX1 input data 011: RX2 input data 100: RX3 input data 101: RX4 input data 110: RX5 input data 111: RX6 input data
EXTSEL
EMCKP
EDTMUT
RXSEL[2:0]
* GPIOS setting is needed when RMCK, RBCK, RLRCK, and RDATA output are changed with EXTSEL. * RMCK, RBCK, RLRCK, and RDATA output don't change even if it sets to EXTSEL=1 in the state of GPIOS=0.
No.A1056-53/64
LC89058W-E
CCB address: 0xE8; Command address: 13; PLL clock
DI7 1 DI6 1 DI5 1 DI4 0 DI3 0 DI2 0 DI1 CAU DI0 CAL
DI15 FSSEL1
DI14 FSSEL0
DI13 0
DI12 0
DI11 PTOXW1
DI10 PTOXW0
DI9 0
DI8 0
PTOXW[1:0]
Setting of clock switch wait time 00: Clock switching after 2.67ms from when the PLL lock status is identified (initial value) 01: Clock switching after 1.33ms from when the PLL lock status is identified 10: Clock switching after 0.67ms from when the PLL lock status is identified 11: Clock switching after when the PLL lock status is identified MOUT output contents setting (output "L" when PLL unlock status or when a value other than those listed below is calculated) 00: Output "H" when 32kHz/44.1kHz/48kHz is calculated (Initial value) 01: Output "H" when 64kHz/88.2kHz/96kHz is calculated 10: Output "H" when 128kHz/176.4kHz/192kHz is calculated 11: Output "H"when 64kHz/88.2kHz/96kHz or higher is calculated
FSSEL[1:0]
No.A1056-54/64
LC89058W-E
12.3 Read Data 12.3.1 List of read commands * It is possible to read the following items. - Interrupt data output - Monitor output of digital data input status - Input data output when general-purpose I/O parallel input mode is set - Output of fs calculation result - Output of first 48 bits of channel status - Output of burst preamble Pc data Table 12.4 Read Register Map
0xEA DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 DO9 DO10 DO11 DO12 DO13 DO14 DO15 DO16 DO17 DO18 DO19 DO20 DO21 DO22 DO23 DO24 DO25 DO26 RXDET0 RXDET1 RXDET2 RXDET3 RXDET4 RXDET5 RXDET6 0 OERROR OINDET OFSCHG OCSRNW OUNPCM OPCRNW OGPIO OEMPF CSBIT1 IEC1937 DTS51 DTSES 0 0 0 0 0xEB PO0 PO1 PO2 PO3 FSC0 FSC1 FSC2 FSC3 0xEC CS bit0 CS bit1 CS bit2 CS bit3 CS bit4 CS bit5 CS bit6 CS bit7 CS bit8 CS bit9 CS bit10 CS bit11 CS bit12 CS bit13 CS bit14 CS bit15 CS bit16 CS bit17 CS bit18 CS bit19 CS bit20 CS bit21 CS bit22 CS bit23 CS bit24 CS bit25 CS bit26 0xED Pc bit0 Pc bit1 Pc bit2 Pc bit3 Pc bit4 Pc bit5 Pc bit6 Pc bit7 Pc bit8 Pc bit9 Pc bit10 Pc bit11 Pc bit12 Pc bit13 Pc bit14 Pc bit15 -
... ...
... ...
-
-
... ...
-
-
... ...
... ...
-
-
DO45 DO46 DO47
CS bit45 CS bit46 CS bit47
No.A1056-55/64
LC89058W-E
12.3.2 Read register 0xEA (S/PDIF input detection, interrupt flag) output CCB address: 0xEA, Contents of read register output 1
DO7 0 DO6 RXDET6 DO5 RXDET5 DO4 RXDET4 DO3 RXDET3 DO2 RXDET2 DO1 RXDET1 DO0 RXDET0
RXDET0
RX0 input detection 0: No input data in RX0 1: Input data exist in RX0 RX1 input detection 0: No input data in RX1 1: Input data exist in RX1 RX2 input detection 0: No input data in RX2 1: Input data exist in RX2 RX3 input detection 0: No input data in RX3 1: Input data exist in RX3 RX4 input detection 0: No input data in RX4 1: Input data exist in RX4 RX5 input detection 0: No input data in RX5 1: Input data exist in RX5 RX6 input detection 0: No input data in RX6 1: Input data exist in RX6
RXDET1
RXDET2
RXDET3
RXDET4
RXDET5
RXDET6
* For readout of RXDET[10:0], RXMON must be set to "1" beforehand.
No.A1056-56/64
LC89058W-E
CCB address; 0xEA; Contents of read register output 2
DO15 OEMPF DO14 OGPIO DO13 OPCRNW DO12 OUNPCM DO11 OCSRNW DO10 OFSCHG DO9 OINDET DO8 OERROR
OERROR
RERR output (Output status during readout) 0: No transfer error while PLL is locked 1: Transfer error exists or PLL is unlocked Status change of data input pin (clear after readout) 0: No change in status of data input pin 1: Change exists in status of data input pin Result of updating input fs calculation (clear after readout) 0: No update of input fs calculation 1: Input fs calculation is updated Update result of first 48 bits channel status (clear after readout) 0: Not updated 1: Updated
____________
OINDET
OFSCHG
OCSRNW
OUNPCM
AUDIO output (output of status during readout) 0: Non-PCM signal not detected 1: Non-PCM signal detected Update result of burst preamble Pc (clear after readout) 0: Not updated 1: Updated Update result of input date when the general-purpose I/O parallel input mode is set (GPIOS=0) (clear after readout) 0: Not updated 1: Updated Channel status emphasis detection (output of status during readout) 0: No pre-emphasis 1: 50/15s pre-emphasis exists
____________
OPCRNW
OGPIO
OEMPF
*
Concerning OERROR and OUNPCM, the status of RERR and AUDIO that are subject to RESEL setting are read _______ regardless of the INToutput setting.
No.A1056-57/64
LC89058W-E
CCB address: 0xEA; Contents of read register output 3
DO23 0 DO22 0 DO21 0 DO20 0 DO19 DTSES DO18 DTS51 DO17 IEC1937 DO16 CSBIT1
CSBIT1
Channel status bit 1 detection 0: PCM 1: Non-PCM IEC61937 burst preamble detection 0: Pa, Pb not detected 1: Pa, Pb detected DTS-CD/LD 5.1 channel sync signal detection 0: DTS-CD/LD sync signal not detected 1: DTS-CD/LD sync signal detected DTS ES-CD/LD 6.1 channel sync signal detection 0: DTS ES-CD/LD sync signal not detected 1: DTS ES-CD/LD sync signal detected
IEC1937
DTS51
DTSES
No.A1056-58/64
LC89058W-E
12.3.3 Read register 0xEB (General-purpose I/O parallel input contents, fs calculation results) output CCB address: 0xEB, Contents of read register output
DO7 FSC3 DO6 FSC2 DO5 FSC1 DO4 FSC0 DO3 PO3 DO2 PO2 DO1 PO1 DO0 PO0
PO0
Contents input to the GPIO0 pin when the general-purpose I/O parallel input mode is set (GPIOS=0). 0: L 1: H Contents input to the GPIO1 pin when the general-purpose I/O parallel input mode is set (GPIOS=0). 0: L 1: H Contents input to the GPIO2 pin when the general-purpose I/O parallel input mode is set (GPIOS=0). 0: L 1: H Contents input to the GPIO3 pin when the general-purpose I/O parallel input mode is set (GPIOS=0). 0: L 1: H Input data fs calculation result "xxxx": See code table.
PO1
PO2
PO3
FSC [3:0]
Table 12.5 Code Table of Input fs Calculation Result (Ta = 25C, AVDD = DVDD = 3.3 V)
FSC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FSC2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FSC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FSC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Target Frequency Out of range 32kHz 44.1kHz 48kHz 64kHz 88.2kHz 96kHz 128kHz 176.4kHz 192kHz
No.A1056-59/64
LC89058W-E
12.3.4 Read register 0xEC (Readout of first 48 bits of channel status) output * The first 48bits of channel status can be read. * The readout channel status data is output with LSB first. * For readout, set the CCB address to 0xEC. * The channel status data cannot be updated after the CCB address is set. * The relation between the read registers and the channel status data is shown below. Table 12.6 Read Registers of First 48 bits of Channel Status
Register DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 DO9 DO10 DO11 DO12 DO13 DO14 DO15 DO16 DO17 DO18 DO19 DO20 DO21 DO22 DO23 Bit No. Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 Bit 16 Bit 17 Bit 18 Bit 19 Bit 20 Bit 21 Bit 22 Bit 23 Channel number Source number Category code Not defined Contents Application Control Register DO24 DO25 DO26 DO27 DO28 DO29 DO30 DO31 DO32 DO33 DO34 DO35 DO36 DO37 DO38 DO39 DO40 DO41 DO42 DO43 DO44 DO45 DO46 DO47 Bit No. Bit 24 Bit 25 Bit 26 Bit 27 Bit 28 Bit 29 Bit 30 Bit 31 Bit 32 Bit 33 Bit 34 Bit 35 Bit 36 Bit 37 Bit 38 Bit 39 Bit 40 Bit 41 Bit 42 Bit 43 Bit 44 Bit 45 Bit 46 Bit 47 Not defined Word length Not defined Clock accuracy Contents Sampling frequency
No.A1056-60/64
LC89058W-E
12.3.5 Read register 0xED (Burst preamble Pc data) output * The burst preamble Pc data can be read with the demodulation function. * The 16 bit-data of burst preamble Pc are output with LSB first. * For readout, set the CCB address to OxED. * The relation between the read register and burst preamble Pc data is shown below. Table 12.7 Burst Preamble Pc Read Registers
Register DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 DO9 DO10 DO11 DO12 DO13 DO14 DO15 Bit No. Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 Bit stream number Error Data type dependent Information Reserved Contents Data type
No.A1056-61/64
LC89058W-E
12.3.6 Burst Preamble Pc Field * The burst preamble Pc field is shown below. * For the latest information, refer to official specifications. Table 12.8 Burst Preamble Pc Field
Register DO4 to 0 Value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 to 26 27 28 29 to 31 DO6, 5 DO7 0 0 1 DO12 to 8 DO15 to 13 0 NULL data Dolby AC-3 data Reserved Pause MPEG-1, layer 1 data MPEG-1, layer 2, 3 data, or non-extended MPEG-2 Extended MPEG-2 data Reserved MPEG-2, layer 1, low sampling rate MPEG-2, layer 2, 3, low sampling rate Reserved DTS type1 DTS type2 DTS type3 ATRAC ATRACK2/3 Reserved Reserved (MPEG-4, AAC data) MPEG-2, AAC data Reserved Reserved (set to "0") Error flag indicating effective burst payload Error flag indicating burst payload error Data type dependent information Bit stream number. (set to "0") Contents
No.A1056-62/64
LC89058W-E
13 Application Example
12.288MHz 24.576MHz Cx Rd Cc Chip address Chip address Master/Slave Expand/Selector Rp Rp Rp Rp Rf Cc Cx
RERR INT CKST AUDIO MOUT DGND DVDD
M-computer
HDMI
DO DI CE CL XMODE DGND Cc DVDD GPIO0 GPIO1 GPIO2 GPIO3 RXOUT2
36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21
DGND
XIN XOUT XMCK DVDD
LC89058W-E
SQFP48 (9X9)
20 19 18 17 16 15 14 13
SDIN SLRCK SBCK RDATA RLRCK DVDD DGND RBCK RMCK AGND AVDD LPF
ADC DAC DSP Cc
Cc
R0 C1 C0
Coaxial Input
Ci Optical Input Cc Cc
Ri
Element Symbol Cc Rp Cx Rf Rd Ci Ri C0 C1 R0
Recommended Parameter 0.1F 10k 1pF to 33pF 1M 150 to 330 0.1F to 0.01F 75
RXOUT1 RX0 RX1 RX2 RX3 DGND DVDD RX4 RX5 RX6 DVDD DGND
Table 13.1 Application Example
Application Power supply de-coupling Function setting Quarts resonator load Oscillation amplifier feedback Oscillation amplifier current limit Coaxial input DC cut Coaxial input termination PLL loop filter PLL loop filter PLL loop filter (: See Section 10.1.1) (: See Section 10.1.1) (: See Section 10.1.1) Ceramic capacitor Remarks Ceramic capacitor Pull-down/pull-up resistor Ceramic capacitor with NP0 characteristics
No.A1056-63/64
LC89058W-E
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above.
This catalog provides information as of November, 2008. Specifications and information herein are subject to change without notice.
PS No.A1056-64/64

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